Viterbi decoder

Details Viterbi decoder Viterbi decoder

1997-02-11

1999-11-09

Chin, Stephen

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

714794, 714795, H03D 100, H04L 2706, G06F 1110

Patent

active

059828226

ABSTRACT:
A viterbi decoder that performs viterbi decoding at a high speed with low power consumption using a memory such as a random access memory as a path selection information storage unit. Adder-comparator-selector (ACS) processing units 13a, 13b time-divisionally perform ACS processing for even and odd number states, respectively, based on the branch metrics from a branch metric computing unit 12 and the path metric of the previous period to produce the path selection information. Eight states of the path selection information storage are collected together by a temporary storage circuit 20 and sent to and written in a path selection information storage unit 15. In the path selection information storage unit 15, the past path selection information is read out during the time other than a write time for the path selection information. The path selection information corresponding to the maximum likelihood states of the path selection information in the path selection information storage unit 15 is read out during the time the ACS processing is performed for all states.

REFERENCES:
patent: 4905317 (1990-02-01), Suzuki et al.
patent: 5291524 (1994-03-01), Itakura et al.
patent: 5710784 (1998-01-01), Kindred et al.

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