Viterbi decoder

Pulse or digital communications – Receivers – Particular pulse demodulator or detector

Reexamination Certificate

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Details

C369S059220

Reexamination Certificate

active

10339321

ABSTRACT:
A path storing circuit has path holding parts at a plurality of stages storing a survivor path and corresponding to times. A majority decision circuit receives output values of three delay circuits including the top and bottom delay circuits each receiving a selected output of a selector out of six delay circuits in the path holding part at the final stage and makes a decision by a majority.

REFERENCES:
patent: 3662338 (1972-05-01), Cain, III
patent: 4715037 (1987-12-01), Yagi
patent: 5901128 (1999-05-01), Hayashi et al.
patent: 5923713 (1999-07-01), Hatakeyama
patent: 6052413 (2000-04-01), Fukuoka
patent: 6594795 (2003-07-01), Satou
patent: 2003/0002419 (2003-01-01), Kuma et al.
patent: 1281296 (2001-01-01), None
patent: 61-128632 (1986-06-01), None
patent: 09-320206 (1997-12-01), None
patent: 10-320931 (1998-12-01), None
patent: 2001-250334 (2001-09-01), None
Tarui, Tadaaki., et al. “Electronic Circuit Course 10.” Digital Computing Circuit, Asakusa Shoten Publishing Co, Ltd., 7th Edition, Mar. 20, 1997, p. 65.

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