Viterbi decoder

Pulse or digital communications – Receivers – Particular pulse demodulator or detector

Reexamination Certificate

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Details

C375S262000, C714S795000, C714S796000

Reexamination Certificate

active

07062000

ABSTRACT:
In a Viterbi decoder a bit range converter (11) is provided for converting a bit range of the branch metric values calculated by a branch metric calculator (1) to meet the number of calculation bits used in an ACS portion (2). The bit range converter (11) is provided between branch metric calculator (1) and ACS portion (2). The decoder reads the received data and calculates the branch metrics, optimizes the branch metrics, changes the path metric, and stores it into the path memory until the frame is completed. When one frame has been completed the decoded result is output by backtracing.

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Notification of Reasons(s) for Refusal mailed Jun. 17, 2003 in corresponding Japanese Application No. 11-021044.
Korean Office Action and English translation thereof mailed Jul. 28, 2004 in corresponding Korean Application No. 10-2002-7004693.
European Search Report mailed May 4, 2005 in corresponding EP application No. 00908047.4-1247-JP0001523.
Shung et al, “VLSI Architectures for Metric Normalization in the Viterbi Algorithm”, International Conference on Communications including Supercomm Technical Sessions, Atland, Apr. 15-19, 1990, New York, IEEE, US, vol. VOL 4, Apr. 15, 1990, pp. 1723-1728.

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