Viterbi ACS unit with renormalization

Details Viterbi ACS unit with renormalization Viterbi ACS unit with renormalization

1993-03-29

1994-09-20

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

375 17, 375 42, 371 43, H04L 2706

Patent

active

053496086

ABSTRACT:
In a Viterbi decoder including an add-compare-select (ACS) processor, speed is enhanced without loss of performance by maintaining a dynamic cumulative metric range for computed state metrics. Current state metrics are added to new branch metrics to obtain two computed metrics, and the smaller of the two computed metrics is stored along with previously computed state metrics. The stored state metrics are compared with a selected scale factor, for example one-half maximum scale factor, and all current state metrics are rescaled when the minimum stored metric value exceeds the selected scale factor.

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patent: 4905317 (1990-02-01), Suzuki et al.
patent: 5027374 (1991-06-01), Rossman
Fettweis, et al., "High-Rate Viterbi Processor: A Systolic Array Solution," IEEE Journal of Sel. Areas in Comm., vol. 8, No. 8, Oct. 1990, pp. 1520-1534.
Fettweis, et al., "A 100Mbit/s Viterbi Decoder Chip: Novel Architecture and its Realization," ICC'90, Paper No. 257, Session 307.4, Atlanta, Ga., Apr. 16-19, 1990, pp. 1-5.
Gulak, et al., "VLSI Structures for Viterbi Receivers: Part I-General Theory and Applications," IEEE J. on Sel. Areas in Comm., vol. SAC-4, No. 1, Jan. 1986, pp. 142-154.
Frenette, et al., "Implementation of a Viterbi Processor for a Digital Communications System with a Time-Dispersive Channel," IEEE J. on Sel. Areas of Comm., vol. SAC-4, No. 1, Jan. 1986, pp. 160-167.

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