Visual frame buffer architecture

Details Visual frame buffer architecture Visual frame buffer architecture

1992-06-19

1994-09-06

Shaw, Dale M.

395164, G06F 1520

Patent

active

053455541

ABSTRACT:
An apparatus for processing visual data includes a first video random access memory (VRAM) for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first VRAM by a data bus and a storage bus. The apparatus is capable of receiving at least a second VRAM for storing at least a second bit plane of visual data in at least a second format different from the first format. The received VRAMs are coupled to the graphics controller by data and storage busses. The visual data stored on the VRAMs are merged into a pixel stream which is then converted to analog form by a digital to analog converter. Data transfer addresses are generated for each of the VRAMs simultaneously, sequentially or in overlapping timed relationship.

REFERENCES:
patent: 4494144 (1985-01-01), Brown
patent: 4737916 (1988-04-01), Ogawa et al.
patent: 4791112 (1988-02-01), Callemyn
patent: 4979130 (1990-12-01), Li et al.
patent: 4991110 (1991-02-01), Hannah
patent: 5151975 (1992-09-01), Shiraki et al.
patent: 5179639 (1993-01-01), Taaffe

Affiliated with

Also associated with

Rating

Visual frame buffer architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Visual frame buffer architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Visual frame buffer architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1335470