Visual frame buffer architecture

Details Visual frame buffer architecture Visual frame buffer architecture

1995-04-20

1996-08-13

Tung, Kee Mei

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

395162, 345185, 345201, G06F 1200

Patent

active

055465315

ABSTRACT:
A graphics controller concurrently reads two streams of visual data stored in memory, where one of the streams is in a subsampled data format. The graphics controller upsamples the subsampled visual data and merges the two data streams to generate a merged pixel stream for display. One data stream may be graphics data in an 8-bit CLUT format and the other data stream may be video data in an 8-bit YUV format. The graphics controller may apply chromakeying to generate the merged pixel stream.

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