Motion video signal processing for recording or reproducing – Local trick play processing – With randomly accessible medium
Reexamination Certificate
1999-04-27
2004-01-06
Boccio, Vincent (Department: 2615)
Motion video signal processing for recording or reproducing
Local trick play processing
With randomly accessible medium
C386S349000, C348S231500
Reexamination Certificate
active
06674956
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a VISS signal detecting method enabling detection of a VISS signal of a video tape by software in a microcomputer which can not use VISS detecting function of hardware, and a storage medium storing a computer program detecting the VISS signal.
2. Description of the Related Art
A VISS signal is a signal generated by writing a given amount (number within a standard) of VISS pulses, and is used for finding a video recording start position. In general, in a versing-up operation called as an index search or so forth, a video tape traveling at high speed is scanned to perform normal reproduction from a detecting position of the VISS signal. A VISS system is a system detects a VISS pulse generated by varying a falling edge timing of a phase position detecting signal recorded upon VTR recording and make a judge that the VISS signal is found when twenty-five or more VISS pulses are sequentially detected (under standard, skipping of the pulse in the extent of one pulse in sequential detection of the VISS pulses is permitted, judgment is made that the VISS signal is detected when twenty-five pulses is detected in detection of more than or equal to 90% of write pulses).
Discussion will be given about occurrence of delay at an interruption process start timing with reference to a timing chart of FIG.
9
. At a timing
901
of
FIG. 9
, execution of a process A is initiated. When execution demand of a process B having higher preference than the process A and a process C having lower preference than the process A occur during execution of the process A, the process A on execution is interrupted, the process B is initiated and the process C is placed in waiting for process initiation.
When the process B is completed, execution of the process A having higher preference than the process C is resumed. The process C is thus executed after completion of the process A. In this condition, assuming that execution demand for an interrupt process D having preference lower than the process A but higher than the process C occurs at a timing
903
, execution of the interrupt process D is initiated immediately after completion of the process A. Thus, execution of the process C is withheld until completion of the interrupt process D. In this case, a period
910
from occurrence of the execution demand for the process C to actual initiation of execution is referred to as interruption delay period.
In a VTR system, disturbance of drive control of a motor should results in distortion of the image. Accordingly, it is ideal to set preference of an interrupt process of motor drive control as high as possible. On the other hand, in order to minimize the interruption delay period in the motor drive control process, interrupt processes having higher priority than the motor drive control process are required to shorten the process periods as short as possible.
FIG. 10
is a timing chart showing the conventional VISS signal detecting operation, and
FIG. 11
is a block diagram showing an example of a register construction within a microcomputer used for conventional VISS pulse and
FIG. 12
is an illustration showing a VISS pulse standard.
Operation of VISS detection using the conventional hardware will be discussed with reference to
FIGS. 10
to
12
. In
FIG. 11
, a timer
1103
measures a period of one cycle of a phase position detection signal and is cleared by interruption of the phase position detection signal. On the other hand, a count value of the timer
1103
is stored in a comparing register
1102
.
At first, on the basis of a period of the phase position detection signal before a measurement timing
1005
for measuring a period of the phase position detection signal, a VISS signal judgment timing during a period of the phase position detection signal after the measurement timing is derived. Here, the VISS signal judgment timing is a timing elapsed one half (50%) of the phase position detection signal period
1001
from the measurement timing
1005
. Namely, on the basis of a level of the phase position detection signal at this timing, judgement is made whether the signal is the VISS signal. Namely, at a timing where a count value derived at the immediately preceding phase position detection signal period and stored in the comparing register
1102
and the count value of the timer
1103
are match, the level of the signal waveform of the phase position detection signal is confirmed. When the phase position detection signal level is Hi level, judgment is made that the VISS signal is found. If the phase detection signal level is Low level, judgement is made that the signal is normal pulse. On the other hand, the level of the phase position detection signal at this time is detected by a level detecting portion to store in a VISS detection buffer
1108
. The VISS detection buffer
1108
shores data with shifting to the VISS signal judgment buffer
1108
. When the value resulting by newly taking matches with a value of a signal judgement buffer
1109
, namely the value already set as a pattern upon detection of VISS (in the shown example, when Hi level is detected continuously or sequentially for a times more than or equal to twenty-five times), finding of the VISS signal is judged to generate vector interrupt.
A series of operation set forth above is performed automatically by hardware (only performing setting of pattern of the VISS signal by software), by vector interrupt occurring only upon fining of a VISS mark, the process after fining of VISS is performed by the operation of the hardware.
Setting of the hardware for detection of the VISS signal in the operation set forth above, the VISS signal is detected using rising edge of the phase position detection signal by the detecting edge selector
101
of FIG.
11
. By this, when rising edge of the phase position detection signal is detected, the count value of the timer corresponding to one cycle of the phase position detection signal is stored in the register
1102
. Subsequently, the timer
1103
is cleared. A period corresponding to 50% of the count value stored in the register
1102
is stored in the register
1104
. In the example of
FIG. 10
, at a timing
1005
. a length of the period
1001
is the value of the timer
1103
stored in the comparing register
1102
.
Then, after clearing the timer
1103
, counting in the timer is progressed again. When the count value of the timer
1103
matches with the value of the register
1104
(namely, a period of 50% of the period
1101
), the phase position detection signal is detected. Then, the level of the phase position detection signal at that time in the level detecting portion
1107
is buffered in the VISS detection buffer
1108
and compared with the value of the preliminarily set VISS signal judgment buffer
1109
.
Repeating the foregoing process, when a result of the level being buffered in the VISS detection buffer
1108
and the value of the VISS signal judgment buffer
1109
match, the interrupt demand
1110
notifying detection of VISS signal is output. The interrupt demand
1110
is detected by the software.
In the prior art set forth above, the VISS signal detection process and the process up to detection of the VISS signal are performed automatically by the hardware. Therefore, delay of the detection position due to other interruption may not be caused. Therefore, detection of the phase position detection signal is possible, and thus, when the phase position detection signal detected can be used in detection of the VISS signal, such detection is effective. However, detection set forth above cannot be used in certain case for the problem discussed below.
At first, it is possible that there is another timer unit using the phase position detection signal as the detection edge (for example, register
1105
of
FIG. 11
) and in the process by the unit, setting for detecting both edges of rising and falling in the phase position detection signal in detection of the phase position detection signal of FIG.
10
. Inter
Boccio Vincent
Fletcher James A
NEC Electronics Corporation
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