Virtual test environment

Details Virtual test environment Virtual test environment

2005-08-23

2005-08-23

Teska, Kevin J. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S019000, C706S006000

Reexamination Certificate

active

06934670

ABSTRACT:
A method of and an apparatus for designing a test environment and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated. An adjustment might be made to the virtual calibration of the virtual test environment and/or to the virtual device, or both, and the design of the actual device might be improved. The invention can be implemented on a properly programmed general purpose processing system or on a special purpose system.

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