Electrical computers and digital processing systems: interprogra – Event handling or event notification
Reexamination Certificate
2009-10-26
2011-12-27
Ho, Andy (Department: 2194)
Electrical computers and digital processing systems: interprogra
Event handling or event notification
C718S102000, C718S104000, C711S147000, C711S148000, C710S260000
Reexamination Certificate
active
08087034
ABSTRACT:
The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, “threads”). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. An event delivery mechanism associates events with respective threads and notifies those threads when the events occur, regardless of which virtual processing unit and/or processor the threads happen to be executing on at the time. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, “thread”) executing within such processor can execute a memory instruction (e.g., an “Empty” or other memory-consumer instruction) that permits the thread to wait on the availability of data generated, e.g., by another thread and to transparently wake up when that other thread makes the data available (e.g., by execution of a “Fill” or other memory-producer instruction).
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Frank Steven J.
Imai Shigeki
Yoneda Terumasa
Frank Steven J.
Ho Andy
Nutter & McClennen & Fish LLP
Powsner David J.
Sharp Kabushiki Kaisha
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