Virtual multi-port RAM employing multiple accesses during single

Details Virtual multi-port RAM employing multiple accesses during single Virtual multi-port RAM employing multiple accesses during single

1994-11-21

1996-07-30

Kim, Matthew M.

Static information storage and retrieval

Magnetic bubbles

Guide structure

365203, 365233, 364DIG1, 3642448, 395431, G05F 1200

Patent

active

055420672

ABSTRACT:
A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.

REFERENCES:
patent: 4845677 (1989-07-01), Chappell et al.
"Special Application Memories"; 8172 IEEE International Solid-State Circuits Conference; 28 (1985) Feb.; 32nd Conf; by Frank E. Barber, Daniel J. Eisenberg, Gloria A. Ingram, Mark S. Strauss and Thomas R. Wik; pp. 44-46.
"Pipelined Clocked Static Memory"; IBM Technical Disclosure Bulletin; vol. 32; No. 38, Aug. 1989, pp. 431-432.
"Pipelined, Time-Sharing Access Technique for a High Integrated Multi-Port Memory"; IEEE Symposium on VLSI Circuits; 1990; by Tsuneo Matsumura, Ken-ichi Endo and Junzo Yamada; pp. 107-108.

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