Patent
1995-12-12
1998-02-24
Moore, David K.
395410, 395412, 395416, 395417, 395418, G06F 0000
Patent
active
057218587
ABSTRACT:
A method and system for memory management and address translation mapping of pools of logical partitions for BAT and TLB entries in a data processing system is provided. An entry in an address translation buffer is created that is associated with a particular block of virtual memory comprised of a plurality of logical partitions that are grouped in one or more pools of logical partitions, wherein the size of each pool of logical partitions is equal to a preselected page size for real memory, and wherein the entry maps each pool of logical partitions to a page of real memory within a sector of real memory, wherein the size of the sector is a function of the size of the associated block of virtual memory. When a logical partition belonging to a particular pool of logical partitions within the particular block of virtual memory is received, the received logical partition is stored in the page of real memory mapped to the particular pool of logical partitions by the entry associated with the particular block of virtual memory. When a logical address for a memory reference to a selected logical partition of a particular block of virtual memory is received, a physical address for the selected logical partition is compiled from an entry of the address translation buffer that is associated with the particular block of virtual memory. The physical address is compiled to address the page in real memory mapped to the pool of logical partitions containing the selected logical partition. The data of real memory in the selected logical partition at the compiled physical address is then retrieved.
REFERENCES:
patent: 5442766 (1995-08-01), Chu et al.
patent: 5450558 (1995-09-01), Ludwig
patent: 5535351 (1996-07-01), Peng
Kemp Jack Wayne
McWilliams G. Jeannette
White Steven W.
Dillon Andrew J.
Henkler Richard A.
International Business Machines - Corporation
Moore David K.
Nguyen Than V.
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