Boots – shoes – and leggings
Patent
1993-10-20
1995-08-29
Gossage, Glenn
Boots, shoes, and leggings
395427, 364DIG1, 3642563, 3642551, 3642463, G06F 1210
Patent
active
054468540
ABSTRACT:
A method and apparatus for providing address translations for a computer system having a virtual memory that is mapped onto physical memory. The apparatus has at least one page frame descriptor (PFD) for describing a contiguous portion of physical memory, at least one translation block (TB) for describing a contiguous portion of virtual memory and a hash list. Each PFD has a base physical address (PA), a PA range beginning at the base PA and a translation entry pointer. Each TB has a base virtual address (VA), a VA range beginning at the base VA, and a page size used to map the VA range of the TB. Each TB also has a header and at least one translation entry. Each header has a TB pointer and each translation entry has a backward pointer. Each translation entry of the TB corresponds to a different equalsized translation range of the VA range of the TB. If the translation range of a translation entry is backed by a physical memory page frame, then the backward pointer of the translation entry points to a describing PFD that describes the corresponding page frame and the translation entry pointer of the describing PFD points to the translation entry. The hash list has a plurality of hash entries. Each hash entry has a translation header pointer and an associated hash index unique to the hash entry.
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Huck, et al., "Architectural Support for Translation Table Management in Large Address Space Machines", Computer Architecture News, vol. 21, No. 2, May 1993, pp. 39-50.
Joshi Vikram P.
Khalidi Yousef A.
Talluri Madhusudhan
Williams Dock G.
Gossage Glenn
Kim Matthew
Sun Microsystems Inc.
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