Virtual memory addressing device

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G06F 932

Patent

active

043762972

ABSTRACT:
A dynamic address translation unit for converting virtual or "logical" address values into real or "physical" address values. A translation Lookaside Buffer (TLB) stores physical addresses corresponding to a limited number of previously translated logical addresses. The available space in the TLB is divided into partitions, each of which stores address translation data for a particular user process. The TLB partition in current use is identified by the value stored in a user partition counter, which is also used to verify that certain process control information (stored in a stack memory location) associated with the partition matches the process control information for that user process which is currently in control of the central processing unit.

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patent: 4068303 (1978-01-01), Morita
patent: 4145738 (1979-03-01), Inoue

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