Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1995-10-31
2000-04-25
Chan, Eddie P.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
712 28, 709240, 370254, 370406, 370409, G06F 1516, H04L 1200
Patent
active
060556188
ABSTRACT:
A multiprocessor computer system includes processing element nodes interconnected with physical communication links in an n-dimensional topology. A flow controlled virtual channel has virtual channel buffers assigned to each physical communication link to store packets containing information to be transferred between the processing element nodes. A non-flow controlled virtual maintenance channel has maintenance channel buffers assigned to each physical communication link to store packets of maintenance information to be transferred between the processing element nodes. The virtual maintenance channel is assigned a higher priority for accessing the physical communication links than the flow controlled virtual channel.
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Wu, M., et
Chan Eddie P.
Cray Research Inc.
Kim Hong
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