Virtual machine system with guest architecture emulation using h

Details Virtual machine system with guest architecture emulation using h Virtual machine system with guest architecture emulation using h

1981-06-15

1984-06-26

Thomas, James D.

Boots, shoes, and leggings

G06F 944, G06F 932

Patent

active

044569548

ABSTRACT:
Translation look aside buffer (TLB) hardware is provided in a central processor (CP) that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Hardware is provided for indicating whether a requested address sent by the CP Instruction Execution (IE) unit for translation is a guest or host
ative request, and for a guest request whether it is a real or virtual address. Intermediate translations for a double-level translation may or may not be inhibited from being loaded into the TLB. Guest entries may be purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces single-level translation hardware to translate each accelerated preferred guest request. A non-accelerated guest request may instead be translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.

REFERENCES:
patent: 4241401 (1980-08-01), De Ward et al.
patent: 4253145 (1981-02-01), Goldberg
patent: 4279014 (1981-07-01), Cassonnet et al.
patent: 4285040 (1981-08-01), Carlson et al.
patent: 4347565 (1982-08-01), Kaneda et al.
patent: 4351024 (1982-09-01), Bradley et al.
patent: 4400769 (1983-08-01), Kaneda et al.

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