Virtual machine coprocessor facilitating dynamic compilation

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C717S140000, C717S151000, C717S153000, C717S154000, C717S158000, C712S034000

Reexamination Certificate

active

07747989

ABSTRACT:
A system includes an abstract machine instruction stream, an execution trace buffer storing information to facilitate dynamic compilation, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a processor coupled to the virtual machine coprocessor and operable to execute the native machine instructions generated by the virtual machine coprocessor. The virtual machine coprocessor updates the execution trace buffer as instructions from the abstract machine instruction stream are processed. In addition, a method for facilitating dynamic compilation includes receiving an instruction to be processed, determining that the instruction marks entry into a basic block, and updating an execution trace buffer.

REFERENCES:
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4787026 (1988-11-01), Barnes et al.
patent: 4839745 (1989-06-01), Tindall
patent: 5937193 (1999-08-01), Evoy
patent: 5953741 (1999-09-01), Evoy et al.
patent: 5970242 (1999-10-01), O'Connor et al.
patent: 6085307 (2000-07-01), Evoy et al.
patent: 6125439 (2000-09-01), Tremblay et al.
patent: 6295645 (2001-09-01), Brewer
patent: 6298434 (2001-10-01), Lindwer
patent: 6330658 (2001-12-01), Evoy et al.
patent: 6332215 (2001-12-01), Patel et al.
patent: 6349377 (2002-02-01), Lindwer
patent: 6609247 (2003-08-01), Dua et al.
patent: 6910207 (2005-06-01), Steinbusch
patent: 6976254 (2005-12-01), Kramskoy
patent: 7107585 (2006-09-01), Berent et al.
patent: 7146613 (2006-12-01), Chauvel et al.
patent: 7210140 (2007-04-01), Lindwer et al.
patent: 2001/0052118 (2001-12-01), Steinbusch
patent: 2002/0019976 (2002-02-01), Patel et al.
patent: 2002/0053072 (2002-05-01), Steinbusch et al.
patent: 2003/0023958 (2003-01-01), Patel et al.
patent: 2003/0028451 (2003-02-01), Ananian
patent: 2003/0061254 (2003-03-01), Lindwer et al.
patent: 2003/0101208 (2003-05-01), Chauvel et al.
patent: 2004/0015896 (2004-01-01), Dornan et al.
patent: 2005/0125790 (2005-06-01), Ben-Yedder et al.
patent: WO 01/71494 (2001-09-01), None
patent: WO 01/71494 (2001-09-01), None
patent: WO 02/19100 (2002-03-01), None
patent: WO 02/27488 (2002-04-01), None
patent: WO 03/027842 (2003-04-01), None
patent: WO 03/029961 (2003-04-01), None
patent: WO 03/034243 (2003-04-01), None
patent: WO 03/036467 (2003-05-01), None
patent: WO 03/088036 (2003-10-01), None
Wong, “Java Processors, Cprocessor Perform Direct Bytecode Execution,” Jul. 2000.
Core Coprocessor Interface Specification, MIPS Technologies Document No. MD00068, Revision 1.15, Entire document: 30 pages, Sep. 25, 2002.
Levy, M., “Java To Go: Part 1,”Microprocessor Report, vol. 15, Archive 2, pp. 1 and 5-7, Feb. 2001.
Levy, M., “Java To Go: Part 2,”Microprocessor Report, pp. 7-8, Mar. 2001.
Levy, M., “Java To Go: Part 3,”Microprocessor Report, pp. 9-11, Mar. 2001.
Levy, M., “Java To Go: Part 4,”Microprocessor Report, vol. 15, Archive 6, pp. 1 and 5-8, Jun. 2001.
MIPS32™ Architecture For Programmers vol. I: Introduction to the MIPS32™ Architecture, MIPS Technologies Document No. MD00082, Revision 0.95, Entire document: 77 pages, Mar. 12, 2001.
MIPS32™ Architecture For Programmers vol. II: The MIPS32™ Instruction Set, MIPS Technologies Document No. MD00086, Revision 0.95, Entire document: 253 pages, Mar. 12, 2001.
MIPS32™ Architecture For Programmers vol. III: The MIPS32™ Privileged Resource Architecture, MIPS Technologies Document No. MD00090, Revision 0.95, Entire document: 109 pages, Mar. 12, 2001.
MIPS64® Architecture For Programmers vol. I: Introduction to the MIPS64® Architecture, MIPS Technologies Document No. MD00083, Revision 2.50, Entire document: 97 pages, Jul. 1, 2005.
MIPS64® Architecture For Programmers vol. II: The MIPS64® Instruction Set, MIPS Technologies Document No. MD00087, Revision 2.50, Entire document: 409 pages, Jul. 1, 2005.
MIPS64® Architecture For Programmers vol. III: The MIPS64® Privileged Resource Architecture, MIPS Technologies Document No. MD00091, Revision 2.50, Entire document: 167 pages, Jul. 1, 2005.
Anand Lal Shimpi, “Intel's NetBurst Architecture—The Pentium 4's innards get a name,” AnandTech (Aug. 20, 2000) 10 pages; downloaded on Jun. 29, 2007, from http://www.anandtech.com/printarticle.aspx?i=1301.
Office Communication, mailed Dec. 27, 2006, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 13 pages.
Office Communication, mailed Jan. 28, 2008, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 12 pages.
Office Communication, mailed Jul. 10, 2008, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 14 pages.
Office Communication, mailed Dec. 22, 2008, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 13 pages.
Office Communication, mailed Jul. 7, 2009, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 17 pages.
Office Communication, mailed Dec. 18, 2009, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 16 pages.
Kissell, K., U.S. Appl. No. 10/637,005, filed Aug. 8, 2003.
Office Communication, mailed Dec. 27, 2006, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 13 pages.
Office Communication, mailed Jan. 28, 2008, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 12 pages.
Office Communication, mailed Jul. 10, 2008, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 14 pages.
Office Communication, mailed Dec. 22, 2008, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 13 pages.
Office Communication, mailed Jul. 7, 2009, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 17 pages.
Office Communication, mailed Dec. 18, 2009, for U.S. Appl. No. 10/637,005, filed Aug. 8, 2003, 16 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Virtual machine coprocessor facilitating dynamic compilation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Virtual machine coprocessor facilitating dynamic compilation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Virtual machine coprocessor facilitating dynamic compilation will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4170023

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.