Virtual instruction cache system using length responsive decoded

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

3642599, 3642595, 36424342, 3642434, 364DIG1, G06F 930

Patent

active

051135159

ABSTRACT:
An instruction buffer of a high speed digital computer controls the flow of instruction stream to an instruction decoder. The buffer provides the decoder with nine bytes of sequential instruction stream. The instruction set used by the computer is of the variable length type, such that the decoder consumes a variable number of the instruction stream bytes, depending upon the type of instruction being decoded. As each instruction is consumed, a shifter removes the consumed bytes and repositions the remaining bytes into the lowest order positions. The byte positions left empty by the shifter are filled by instruction stream retrieved from one of a pair of prefetch buffers (IBEX, IBEX2) or from a virtual instruction cache. These prefetch buffers are arranged to hold the next two subsequent quadwords of instruction stream and provide the desired missing bytes. The IBEX prefetch buffer is filled from the instruction cache after being emptied, but prior to those particular bytes being requested to fill the instruction decoder. This two level prefetching allows the relatively slow process of cache access to be performed during noncritical time. The instruction decoder is not stalled, waiting for a cache refill, but can ordinarily obtain the desired bytes of instruction stream from the prefetch buffer.

REFERENCES:
patent: 3771138 (1973-11-01), Celtruda
patent: 4454578 (1984-06-01), Matsumoto et al.
patent: 4500958 (1985-02-01), Kubo et al.
patent: 4521850 (1985-06-01), Wilhite
patent: 4602368 (1986-07-01), Circello
patent: 4626988 (1986-12-01), George
patent: 4635194 (1987-01-01), Burger
patent: 4719570 (1988-01-01), Kawabe
patent: 4722050 (1988-01-01), Lee
patent: 4725947 (1988-02-01), Shonai
patent: 4755933 (1988-07-01), Teshima
patent: 4853840 (1989-08-01), Shibuya
patent: 4860192 (1989-08-01), Sachs
patent: 4879687 (1989-11-01), Okamoto
patent: 4953121 (1990-08-01), Muller
patent: 4989140 (1991-01-01), Nishimakai
Fossum et al., "an Overview of the VAX 8600 System," Digital Equipment Technical Journal, No. 1, Aug. 1985, pp. 8-23.
Troiani et al., "The VAX 8600 I box, A Pipelined Implementation of the VAX Architecture," Digital Technical Journal, No. 1, Aug. 1985, pp. 24-42.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Virtual instruction cache system using length responsive decoded does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Virtual instruction cache system using length responsive decoded, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Virtual instruction cache system using length responsive decoded will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2427785

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.