Virtual-ground flash EPROM array with reduced cell pitch in the

Details Virtual-ground flash EPROM array with reduced cell pitch in the Virtual-ground flash EPROM array with reduced cell pitch in the

1996-04-10

1997-02-18

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

36518516, 36518526, 36518527, 36518529, 36523006, 257316, G11C 1604

Patent

active

056046987

ABSTRACT:
In a virtual-ground flash electrically programmable read-only-memory (EPROM), the pitch in the X direction of the floating gates, which are formed over a portion of vertically-adjacent field oxide regions, is reduced by forming the floating gates over continuous strips of vertically-adjacent field oxide. The strips of field oxide are formed in a layer of polysilicon which is formed over a layer of tunnel oxide which, in turn, is formed over the substrate.

REFERENCES:
patent: 5149665 (1992-09-01), Lee
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patent: 5280446 (1994-01-01), Ma et al.
patent: 5326999 (1994-07-01), Kim et al.
patent: 5332914 (1994-07-01), Hazani
patent: 5338956 (1994-08-01), Nakamura
U.S. application Ser. No. 07/988,293, Bergemont.
U.S. application Ser. No. 07/830,938, Bergemont.

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