Virtual ground EPROM structure

Details Virtual ground EPROM structure Virtual ground EPROM structure

1999-07-22

2001-01-16

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185160, C365S185220

Reexamination Certificate

active

06175519

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to an improved virtual ground structure for erasable programmable read-only memory devices (EPROMS).
2. Description of the Related Art
Erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM) and Flash memory are classes of floating gate memory devices. More particularly, these floating gate memory devices are programmable memory devices which use floating gates as charge storage layers. These devices are based on a memory transistor, consisting of a source, channel, and a drain with a floating gate over the channel and a control gate isolated from the floating gate. Programming a cell requires charging the floating gate with electrons, which increases the turn on threshold of the memory cell. Flash EPROMS typically use a “hot electron” programming technique to charge the cells. When programmed, the cell will not turn on, i.e. it remains non-conductive, if a read potential is applied to its control gate. To erase the cell, electrons are removed from the floating gate in order to lower the threshold. With a lower threshold, the cell will now turn on when a read potential is applied to the control gate. Conventionally, hot electron programming is performed by ramping up the drain voltage or the gate voltage. In other words, the source voltage is first shorted to ground, and then the drain (or gate) voltage is increased. Finally, the gate (or drain) voltage is applied.
One known type of EPROM structure is a virtual ground structure. For a conventional virtual ground structure
10
shown in
FIG. 1
, as disclosed in U.S. patent application Ser. No. 08/918,796 entitled “APPARATUS AND METHOD FOR PROGRAMMING VIRTUAL GROUND EPROM ARRAY CELL WITHOUT DISTURBING ADJACENT CELLS,” shrinking the cell size does not result in a reduction in array size because the metal pitch is the dominant factor. The principal reason is that the buried bit lines and ground lines are formed by an N+diffusion and are connected to individual metal lines. However, the metal line widths and spacing are difficult to shrink due to yield considerations (i.e. further reductions in line widths or spacing would lower the yield to unacceptable levels).
FIG. 2
illustrates a prior art cell for a mask programmable read-only memory (MROM) application, as disclosed in U.S. Pat. No. 5,202,848. By combining one metal line with two bit line selection transistors (BLT), also known as band select transistors, the cell size can keep shrinking because the metal pitch is no longer the dominant limiting factor. For this structure, one metal pitch is connected to two buried diffusion lines. However, if a similar structure is applied to EPROMS, the device would suffer from programming disturbances for the adjacent cells. For example, if a high voltage is applied to bitline
1
when cell
1
is programmed, cell
2
will also experience a high voltage causing a possible disturbance to the data in cell
2
.
Therefore, it would be desirable to have an improved EPROM structure whose cell size can shrink independent of the metal pitch and which does not produce programming disturbances on adjacent cells.
SUMMARY OF THE INVENTION
In a virtual ground semiconductor memory device such as an EPROM or a Flash EPROM, a program disturb inhibited unit is operatively connected to a memory array. The memory array comprises a plurality of rows of memory cells, with each cell in a row connected to a common cell word line (SWL). The memory array further includes a plurality of metal virtual ground and bit lines, with at least two bit line selection transistors (BLT) connected to each of the metal lines.
The program disturb inhibited connects to each virtual ground line and each bit line. In this structure, one metal pitch is connected to two buried diffusion lines. In a preferred embodiment, four block selection lines (BWL) lines are connected to control the bit line selection transistors. The program inhibited unit includes a plurality of program disturb inhibited transistors, wherein each transistor is connected between a virtual ground and a bit line. A DWL and a DWR dummy line are connected to control the plurality of program disturb inhibited transistors. The bit line transistors or the program disturb inhibited transistors may be either buried type transistors or normal peripheral transistors.
In order to perform a programming operation, the program pulses are divided into a program disturbance inhibited period and a programming period. The program disturbance inhibited unit prevents adjacent memory cells from being disturbed by a programming operation on an adjacent cell.
By combining the program disturb inhibit unit with the memory array, the conventional array structure which has only been suitable for MROM applications can be applied to an EPROM or a Flash EEPROM, thus allowing the cell size to be reduced.


REFERENCES:
patent: 5202848 (1993-04-01), Nakagawara
patent: 5241497 (1993-08-01), Komarek
patent: 5463586 (1995-10-01), Chao et al.
patent: 5553020 (1996-09-01), Keeney et al.
patent: 5563822 (1996-10-01), Yiu et al.
patent: 5590076 (1996-12-01), Haddad et al.
patent: 5677216 (1997-10-01), Tseng
patent: 5734602 (1998-03-01), Guritz et al.
patent: 5959892 (1999-09-01), Lin et al.
patent: 6064592 (2000-05-01), Nakagawa et al.

Affiliated with

Also associated with

Rating

Virtual ground EPROM structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Virtual ground EPROM structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Virtual ground EPROM structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2461572