Virtual ground circuit for reducing SRAM standby power

Details Virtual ground circuit for reducing SRAM standby power Virtual ground circuit for reducing SRAM standby power

2008-05-27

2008-05-27

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S226000

Reexamination Certificate

active

07379374

ABSTRACT:
A method of operating a memory circuit having a plurality of blocks of memory cells (400-404) is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first block of memory cells (400) is selected in response to a first address signal (RAY0). A row of memory cells (430-436) in the first block of memory cells is selected in response to a second address signal (RAX0). A first voltage is applied to a first power supply terminal (412) of the first block of memory cells in response to the first address signal. A second voltage different from the first voltage is applied to a first power supply terminal (412) of another block of memory cells (402) of the plurality of blocks of memory cells. Data is retained in the other block of memory cells.

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patent: 5644576 (1997-07-01), Bauchot et al.
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Wei et al., “Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits,” 35thDesign Automation Conference Proc., 489-494 (1998).
Powell et al., “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories,” Proc. Int. Symp. Low Power Electronics and Design (ISLPED), 90-95 (2000).
Agarawal et al., “A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron,” IEEE J. Solid-State Circuits, vol. 38, No. 2, 319-328 (Feb. 2003).

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