Virtual contiguous FIFO for combining multiple data packets into

Details Virtual contiguous FIFO for combining multiple data packets into Virtual contiguous FIFO for combining multiple data packets into

1997-04-30

2000-01-18

Nguyen, Chau

Multiplex communications

Pathfinding or routing

Through a circuit switch

370391, 370414, H04L 1256, H04L 1250

Patent

active

060163151

ABSTRACT:
A virtual contiguous system for combining multiple and arbitrarily-sized and aligned digital data packets from a PCI bus to a DSP circuit is disclosed. Information from the PCI bus is supplied directly to a plurality of FIFO RAM memory units. Each packet of digital data includes data packet descriptors identifying at least the start address for each data packet and the size of each data packet. The system utilizes this information to operate a read pointer and a write pointer to remove data from the FIFO RAM memory units on a sequential bit-by-bit basis and to supply said data packets to said RAM memory units by means of a write pointer operated by said control circuit. The information transfer is managed on the read side of the FIFO RAM memory units with minimal processing on the write side.

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