Virtual channel synchronous dynamic random access memory

Details Virtual channel synchronous dynamic random access memory Virtual channel synchronous dynamic random access memory

2000-12-21

2001-12-11

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S051000, C365S189070

Reexamination Certificate

active

06330205

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a virtual channel synchronous dynamic random access memory.
A conventional virtual channel synchronous dynamic random access memory is disclosed in Japanese laid-open patent publication No. 8-180698. Operations of the conventional virtual channel synchronous dynamic random access memory will be described with reference to the drawings.
FIG. 1
is a view illustrative of an array structure of the conventional virtual channel synchronous dynamic random access memory. The conventional virtual channel synchronous dynamic random access memory has the array structure of memory cells (M-CELL), main decoders (XDEC)
34
, sense amplifiers (SA)
32
, word drivers (WDRV)
31
and cross sections (CROSS)
36
.
FIG. 2
is a fragmentary enlarged view illustrative of a partial array structure surrounded by a broken line
35
of the conventional virtual channel synchronous dynamic random access memory shown in FIG.
1
. Four memory cells (M-CELL)
43
are separated by a cross section (CROSS)
49
, word drivers (WDRV)
41
, and sense amplifiers (SA)
42
. Each of the word drivers (WDRV)
41
comprises repeated basic word driver cells (WDRV) and a redundancy word driver (RED-WDRV)
46
. Each of the sense amplifiers (SA)
42
comprises repeated basic sense amplifier cells (SA) and a redundancy sense amplifier (RED-SA)
45
.
FIG. 3
is a circuit diagram illustrative of a circuit configuration of a basic word driver cell included in the word driver shown in FIG.
2
. The basic word driver cell has a first input of a single MainWord outputted from the main decoder (XDEC)
44
and second to fifth inputs of four RA signals (RA
1
, RA
2
, RA
3
, and RA
4
) as well as first to fourth outputs (WD
1
-m
1
, WD
2
-m
1
, WD
3
-m
1
, and WD
4
-m
1
) of Words corresponding to 2-bits from least significant of Row address.
The size o the basic word driver cells of the word driver (WDRV)
41
depends on a pitch of word lines extending over the memory cell (M-CELL)
43
.
In order to reduce the height of the basic word driver cell and further to accommodate the four RA signals into the basic word driver cell, the word driver (WDRV) is structured so that basic word driver cells of the adjacent word drivers
53
and
54
are symmetrically arranged with reference to a line and an RA signal is commonly used for the adjacent two basic word driver cells of the adjacent word drivers
53
and
54
.
FIG. 4A
is a circuit diagram illustrative of the symmetrical arrangements of the basic word driver cells of the adjacent word drivers.
FIG. 4B
is a circuit diagram illustrative of word driver basic cells and an adjacent redundancy word driver basic cell in the arrangements of FIG.
4
A.
FIG. 5
is a schematic view illustrative of a conventional semiconductor memory device having an alternating alignment of the word drivers and the memory cells, wherein one of main-words is replaced with a redundancy (RED)
81
. Namely, in the prior art, if any defective bit is present in the memory cell accessible from the single Word, then the Main-Word having the defective bit is not used, and in place, the defective Main-Word is changed into a redundancy Main-Word for the redundancy.
It is, however, necessary for this conventional method to switch not only the defective Word but also the non-defective Word which uses the same Main Word as the defective Word. This means that the replacement efficiency is deteriorated.
In accordance with the virtual channel synchronous dynamic random access memory, in order to have solved the above disadvantage, the RA signal of the redundancy word driver is separated from the RA signal of the word driver, so that both the defective Main-Word and the redundancy Main-Word are used to switch the RA signal only to the defective Word, whereby only the defective Word is selectively replaced with the redundancy Word (RED).
As described above, in accordance with the virtual channel synchronous dynamic random access memory, the RA signal of the redundancy word driver is separated from the RA signal of the word driver, for which reason it is difficult that the RA signal is commonly used for the word driver and the redundancy word driver.
FIG. 6A
is a schematic diagram illustrative of the conventional structure of the word driver (WDRV) and a redundancy word driver (RED-WDRV) adjacent to the word driver.
FIG. 6B
is a diagram illustrative of the conventional placement of the semiconductor memory device. The word driver (WDRV) and the redundancy word driver (RED-WDRV) are separated by a distance (
2
a
+
2
b
). The above conventional technique has the following two problems.
First, the distance between the word driver (WDRV) and the redundancy word driver (RED-WDRV) is widen, whereby structural elements of the redundancy word driver (RED-WDRV) and interconnections extending over the cross region (CROSS). It is difficult that the signal in the sense amplifier SA passes through the cross region (CROSS). A device formation region in the cross region (CROSS) is also reduced.
Second, a displacement of the redundancy word driver (RED-WDRV) causes that a Word-input position of the memory cell M-CELL and a Word-output position of the redundancy word driver (RED-WDRV) are displaced by the distance (
2
a
+
2
b
).
In the above circumstances, it had been required to develop a novel semiconductor memory device free from the above problem.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel semiconductor memory device free from the above problems.
It is a further object of the present invention to provide a novel virtual channel synchronous dynamic random access memory free from the above problems.
The present invention provides a semiconductor memory device comprising : memory cells; main decoders decoding address signals; sense amplifiers for reading out informations from the memory cells; and word drivers for driving the memory cells, wherein a row address controlled by a single main word line in a basic cell in the word driver, and two of the main word line of the row address are made correspond to a half of lower-order 2-bits of the row address, and a word driver signal is placed inside of the basic cell of the word driver to prevent the word driver signal from being commonly used to adjacent two of the basic cell.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.


REFERENCES:
patent: 5148397 (1992-09-01), Kokubum

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