Virtual channel DRAM

Details Virtual channel DRAM Virtual channel DRAM

2000-12-04

2002-08-27

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S201000

Reexamination Certificate

active

06442097

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a virtual channel DRAM; and, more particularly, to a virtual channel DRAM capable of reducing test time for an entire chip by providing data transfer between a channel and a number of segment blocks all with a predetermined command mode.
PRIOR ART OF THE INVENTION
FIG. 1
is a diagram for explaining data transfer between segments and channels in a conventional virtual channel DRAM.
A segment is a group of memory cells, each of which is connected t o a pair of bit line bus BL/BLB by an active command, and an entire cell array are divided into a number of segments. A channel refers to a register for storing data of the whole cell array or some part thereof and they are connected to the bit line bus BL/BLB in response to the active command. In the virtual channel DRAM, the number of total bits for one segment is identical to that for one channel so that data transfer is performed between the segment and the channel.
FIG. 2
is a diagram of conventional segments
10
_
0
to
10
_N shown in FIG.
1
. The whole cells, that are connected to the bit line bus BL/BLB by the active command, are divided in to a number of blocks.
FIG. 3
is a diagram of a conventional segment selector
20
shown in
FIG. 1
, in which this is s electively connected to the bit line bus BL/BLB in one of the segments
10
_
0
to
10
_N. As shown in
FIG. 3
, in the segment selector
20
, an NMOS transistor is coupled respectively between each bit line bus BL/BLB and each data transfer bus and switched by a segment selection signal SGS<N>.
The segment selection signal SGS<
2
> among SGS<
0
>, . . . , SGS<N> transits to logic high when the bit line bus BL/BLB of a segment<
0
> block is connected to the data transfer bus. The segment selection signal SGS<N> transits to logic high when bit line bus BL/BLB of a segment<N> block is coupled to the data transfer bus.
FIG. 4
is a diagram of a conventional channel selector
40
shown in
FIG. 1
, that selectively couples a channel bus CRG/CRGB bus in one of a number of channels to the data transfer bus. As shown in
FIG. 4
, in the segment selector
40
, a NMOS transistor is coupled between each channel bus CRG/CRGB and each data transfer bus, respectively, and switched by a channel selection signal CS<M>.
The channel selection signal CS<
0
> among channel selection signal CS<
0
>, . . . , CS<N> transits to logic high when the channel bus CRG/CRGB of a channel<
0
> is coupled to the data transfer bus. And the channel selection signal CS<M> transits to logic high when the channel bus CRG/CRGB of a channel<M> channel is coupled to the data transfer bus.
FIG. 5
is a diagram of conventional channels
50
_
0
to
50
_N shown in
FIG. 1
, that stores temporarily data transferred among the bit line bus BL/BLB, the data transfer bus and the channel bus CRG/CRGB.
FIG. 6
is a circuit diagram of a segment selection signal (SGS) generator
30
shown in
FIG. 1
, that generates segment selection signal SGS<
0
>, . . . , SGS<N> for selectively coupling bit line bus BL/BLB in one of a number of segments and the data transfer bus;
The conventional SGS signal generator
30
includes: NAND gates NA
0
, NA
2
, . . . , to which SAB<
0
>, SAB<
1
>, . . . , SAB<K> are applied; inverters INV
0
, INV
2
, . . . , for inverting outputs of the NAND gates NAD, NA
2
, . . . , to provide segment selection signals SGS<
0
>, SGS<
2
>, . . . ; NAND gates NA
1
, NA
3
, . . . , to which SA<
0
>, SAB<
1
>, . . . , SAB<K>; and inverters INV
1
, INV
3
, . . . , for inverting outputs of the NAND gates NA
1
, NA
3
, . . . , to provide the segment selection signals SGS<
1
>, SGS<
3
>, . . . .
Here, segment address signals SA<
0
>, SAB<
0
>, SA<
1
>, SAB<
1
>, . . . , SA<N>, SAB<N> are applied from an external circuit for selecting the segment. The segment address signal SA<
0
> becomes logic high when the address signal determining logic of the segment address signals SA<
0
> and SAB<
0
> among the address signals is logic high. On the contrary, the segment address bar signal SAB<
0
> becomes logic high when the address signal determining logic of SA<
0
> and SAB<
0
> among the address signals is logic low.
The segment address signal SA<K> becomes logic high when the address signal determining logic of SA<K> and SAB<K> among the address signals is logic high. On the contrary, the segment address bar signal SAB<K> becomes logic high when the address signal determining logic of SA<K> and SAB<K> among the address signals is logic low.
The segment selection signal SGS<
0
>, which becomes logic high when the bit line bus BL/BLB of the segment<
0
> block is connected to the data transfer bus, becomes logic high when the segment address bar signals SAB<
0
>, SAB<
1
>, . . . , SAB<K> become logic high. And, the segment selection signal SGS<N> that becomes logic high when the bit line BL/BLB of the segment<N> block is connected to the data transfer bus becomes logic high when the segment address signals SA<
0
>, SA<
1
>, . . . , SA<K> become logic high.
A command signal BGM becomes logic high when a data transfer between the segment and the channel is performed.
However, in the data transfer between the segments and the channels in the conventional virtual channel DRAM, one of the segments always corresponds to one of the channels. Therefore, the command for data transfer from the channel to the segment should be inputted N times to transfer data from one channel to N segments.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a virtual channel DRAM capable of reducing chip test time by configuring logic in such a way to simultaneously transfer data from a channel to N segments with a predetermined external command input.
In accordance with an aspect of the present invention, there is provided a virtual channel DRAM comprising; a number of segments for dividing a cell coupled to bit line by an active command is divided into a number blocks; a number of segment selecting units for selectively coupling the bit line in one of the segments to a data transfer bus; a number of channels for temporarily storing data transferred among the bit line, the data transfer bus and a channel bus line; a number of channel selecting units for selectively coupling the channel bus line in one of the channels to the data transfer bus; and a control signal generating unit for generating a first control signal used for selectively coupling the bit line in one of the segments to the data transfer bus and used for simultaneously coupling the bit lines of all segments to the data transfer bus in a predetermined external command mode.
The control signal generating unit includes: even order NAND gates at input stage, to each of which address signals applied from external to select one of the segments and a second control signal; odd order NAND gates at input stage, to each of which the address signals applied from external to select one of the segments and the second control signal; even order NAND gates at output stage, to each of which outputs of the even order NAND gates at the input stage and a third control signal and each of which provides the first control signal; and odd order NAND gates at output stage, to each of which outputs of the odd order NAND gates at the input stage and the third control signal and each of which provides the first control signal.
The second control signal becomes logic high when a command corresponding to data transfer between the segments and the channels is applied.
The third control signal becomes logic high in an external command mode for a predetermined test in which data is transferred from the channels to the segments.
In accordance with another aspect of the present invention, there is provid

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