Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-01-12
2003-05-06
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S534000
Reexamination Certificate
active
06559708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit intended to reduce its power dissipation by controlling power supplies to an internal circuit in response to active and sleep periods of the internal circuit.
2. Description of the Prior Art
Recent developments in portable or mobile equipment have caused requirements of low power consumption semiconductor integrated circuits. For example, as shown in JP-A 7/212218, it has been proposed to provide a semiconductor integrated circuit with a power supply switch in which a power supply to an internal circuit is provided in an active period to operate the internal circuit, while the power supply to the internal circuit is stopped in a sleep period which don't have to operate the internal circuit, e.g. in no operation by users. Particularly, by employing a MTCMOS (Multi-threshold CMOS) in which a threshold voltage of transistors constituting the power supply switch is larger than that of transistors constituting an internal circuit, the internal circuit which can operate by a low voltage power supply is achieved and leakage currents at the sleep period may be decreased.
As to the MTCMOS, a semiconductor further improved is described in JP-A 11/214962.
FIG. 11
illustrates a first semiconductor integrated circuit disclosed in JP-A 11/214962. The first semiconductor integrated circuit includes: a p-channel field effect transistor (hereinafter, referred to as pMOS transistor) QA
1
as a power supply switch which is connected between a power supply line VDD and a virtual power supply line VA
1
; a n-channel field effect transistor (hereinafter, referred to as nMOS transistor) QB
1
as a power supply switch which is connected between a power supply line GND and a virtual power supply line VB
1
; a diode D
1
which is connected between the power supply line VDD and the virtual power supply line VA
1
; and a diode D
2
which is connected between the power supply line GND and the virtual power supply line VB
1
. An internal circuit is connected between the virtual power supply lines VA
1
, VB
1
which feed power supplies for operation. The internal circuit includes pMOS transistors Q
3
, Q
4
and nMOS transistors Q
5
, Q
6
each of which has an absolute value of the threshold voltage smaller than that of each of the transistors QA
1
, QB
1
.
The power supply line is applied with a voltage having a low voltage value LVDD around 1.0 V in an active period which operates the internal circuit and a voltage having a high voltage value HVDD of 3.3 V in a sleep period which does not use the internal circuit. The transistors QA
1
, QB
1
are controlled by control signals CS
1
, CSB
1
so as to be turned on simultaneously when the internal circuit is in the active period and turned off simultaneously when in the sleep period.
When the internal circuit is especially in the sleep period, each of the transistors Q
3
-Q
6
is reversely biased to the source in a direction to increase the absolute value of the threshold voltage by the diodes D
1
, D
2
. When the internal circuit includes a sequential circuit such as a latch circuit, data latched in the sequential circuit in the active period may be latched without losses of the data in the sleep period, and a leakage current in the sleep period may be controlled.
FIG. 12
illustrates a second semiconductor integrated circuit disclosed in JP-A 11/214962. As only a part different from
FIG. 11
is described, the second semiconductor integrated circuit includes: a pMOS transistor QA
2
, connected between a power supply line VDD
1
and a backgate power supply line VA
2
, to be turned on/off simultaneously with a transistor QA
1
; and a pMOS transistor QA
3
, connected between a backgate power supply line VA
2
and a power supply line VDD
2
, to be turned on/off complementarily with the transistor QA
1
. A diode D
1
is connected between a virtual power supply line VA
1
and the backgate power supply line VA
2
. A voltage having a voltage value LVDD is applied to the power supply line VDD
1
, while a voltage having a voltage value HVDD higher than the voltage value LVDD is applied to the power supply line VDD
2
. This second semiconductor integrated circuit also results in the above effect.
In the semiconductor integrated circuit as shown in
FIG. 11
, the virtual power supply line VA
1
ideally becomes a potential level, which is equal to the power supply line VDD, in an active period of an internal circuit. However, in reality, a voltage drop is caused by a wiring resistance of the power supply line VDD, an ON-state resistance of the transistor QA
1
, and so on, and the voltage of the virtual power supply line VA
1
becomes a value of (LVDD−&Dgr;VA
1
). On the other hand, the backgate potential of the transistors Q
3
, Q
4
is LVDD. Since each backgate potential of the transistors Q
3
, Q
4
is higher than the corresponding source potential, the operations of the transistors Q
3
, Q
4
are made slower by an increase of the absolute values of the threshold voltages of these transistors Q
3
, Q
4
. In reality, the voltage of the virtual power supply line VB
1
also becomes a value of &Dgr;VB
1
higher than 0 V by a wiring resistance of the power supply line GND, an ON-state resistance of the transistor QB
1
, and soon. Since each backgate potential of the transistors Q
5
, Q
6
is made lower than that of the corresponding source, the operations of the transistors Q
5
, Q
6
are made slower by an increase of the absolute values of the threshold voltages of the transistors Q
5
, Q
6
. Thus, the operation speed of the internal circuit deteriorates.
On the other hand, in the semiconductor integrated circuit illustrated in
FIG. 12
, in an active period, as described above, the wiring resistance and the ON-state resistance of the transistors QA
1
, QA
2
cause voltage drops of the virtual power supply lines VA
1
, VA
2
from an LVDD value to (LVDD−&Dgr;VA
1
), (LVDD−&Dgr;VA
2
), respectively. Additionally, at this time, the voltage drop of the virtual power supply line VA
1
is remarkably greater than that of the backgate power supply line VA
2
, establishing the relationship of &Dgr;VA
1
>>&Dgr;VA
2
. This is because the leakage current caused from the backgate power supply line VA
2
to the transistors Q
3
, Q
4
via the backgate is negligibly smaller than the active current from the virtual power supply line VA
1
to the VB
1
because of the operation of the internal circuit. The backgate potential is higher than that of each source of the transistors Q
3
, Q
4
, and the operations of the transistors Q
3
, Q
4
are still made slower.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention is to provide a semiconductor integrated circuit which achieves reduced power dissipation in the general circuit while suppressing a performance deterioration of an internal circuit in an active period. A semiconductor integrated circuit of the present invention comprises: a first field effect transistor including one source/drain electrode for receiving as a first power supply voltage, the other source/drain electrode connected to the first virtual power supply line, and a gate electrode for receiving a control signal so as to control ON/OFF of the transistor; a second field effect transistor, having one source/drain electrode connected to the first virtual power supply line and the other source/drain electrode connected to the first backgate power supply line, to be turned on when the first field effect transistor is turned on; and a third field effect transistor having one source/drain electrode connected to the first virtual power supply line and a backgate electrode connected to the first backgate power supply line, and which constructs an internal circuit. This causes a voltage drop to the first virtual power supply line on the first power supply line because of an ON-state resistance of the first field effect transistor and so on. Its forward bias state reduces the absolute value of the threshold voltag
Burns Doane , Swecker, Mathis LLP
Cunningham Terry D.
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