Video timing signal generation circuit

Details Video timing signal generation circuit Video timing signal generation circuit

1995-01-18

1996-12-03

Peng, John K.

Television

Synchronization

Sync generation

348521, H04N 506

Patent

active

055813038

ABSTRACT:
A programmable CPU running at a video display rate, or a sub-multiple thereof, is used to generate the timings by loading control registers on the fly. In a preferred embodiment, a very reduced instruction set is used to generate VSYNC, HSYNC, and CSYNC signals. The CPU executes instructions out of an Instruction SRAM. The CPU's main goal is to load a pair of backing registers before a down counter reaches the value of zero.

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Gerry Kane, "CRT Controller Handbook", 1980 Osborne/McGraw Hill, pp. 4-1 to 4-40.

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