Video stream processing frame buffer controller

Details Video stream processing frame buffer controller Video stream processing frame buffer controller

1986-07-29

1989-01-24

Sheppard, John W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 21R, 358280, 358903, H04N 514

Patent

active

048004316

ABSTRACT:
A video stream processing system frame buffer controller for controlling external dynamic random access memory (DRAM) of a frame buffer and interfacing to the video stream processing signal bus. The frame buffer controller has four interfaces, video input interface, video output interface, memory interface and processor interface. The circuit can input image data from a camera and store the frames in external DRAM. The circuit provides for external processor access to pixels in the frame buffer and for output of the frame or portions of the frame, as well as output of frames in a format of CRT display and external DRAM refresh.

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