Video storage

Television – Basic receiver with additional function – Multimode

Patent

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Details

348555, 348642, 348717, H04N 546

Patent

active

055260578

DESCRIPTION:

BRIEF SUMMARY
This invention relates to the storage and processing of video information for the purpose, in specific examples, of generating a video store or a test pattern.
It is a relatively straightforward matter to construct a store capable of holding one frame of video in YUV or RGB form. Two field stores will suffice. In order to produce a continuous video signal representing, for example, a fixed test pattern, the YUV or RGB output from the field stores will be passed through an encoder operated in PAL, NTSC or SECAM, for example. Encoders, particularly SECAM encoders, are relatively expensive and it would thus be an advantage to have a video store capable of holding luminance and chrominance information already encoded in the desired standard. In circumstances where multi-standard outputs are required, there will be a still greater advantage in storing encoded rather than RGB or YUV information, since the alternative would be to provide essentially three separate encoders.
It will be recognised that in standards such as PAL, NTSC and SECAM, there is a repeating field sequence that extends over more than one frame. This means that a single constant frame of RGB or YUC cannot be represented as a single constant frame of encoded signal. PAL for example has an eight field sequence. An attempt to produce a test pattern in PAL using only two stored fields would introduce chrominance structure which, certainly in the professional environment, would be entirely unacceptable. However, the requirement of eight field storage for a single frame would make the video store extremely expensive. The position is worse if the store is required to provide separate Y and C outputs since two further fields of luminance Storage would be required. A ten field still frame video store would at present hardware costs probably be regarded as prohibitively expensive.
It is an object of this invention to provide improved video storage enabling the generation of a video still, test pattern or other single image which is capable of holding encoded luminance and chrominance signals.
It is a further object of this invention to provide such field storage with economical use of field stores.
In a still further object of certain aspects of this invention to provide for field storage in a manner which can accommodate a range of broadcast standards.
Accordingly, the present invention consists in one aspect in video store means comprising a luminance store for holding one frame of luminance information; chrominance store means for holding at least one frame of chrominance information, the stored luminance and chrominance being encoded to a selected broadcast standard; chrominance channel means communicating with the chrominance store means and providing inverted and non-inverted modes; and channel control means for so controlling the chrominance channel as to provide a continuous video signal in composite or YC form representing a video still, test pattern or other single image.
Advantageously, the chrominance store means comprises first and second chrominance frame stores, the channel control means serving to select both between inverted and non-inverted modes and between first and second chrominance frame stores.
Suitably, the chrominance channel control means can operate, selectively, to produce video signals according to PAL, NTSC or SECAM broadcast standards.
With the use, in one example, of only six fields of storage, the present invention is able to provide video signals according to the PAL eight field sequence, the NTSC four field sequence and the SECAM twelve field sequence. A single piece of hardware can receive video information according to any one of the three standards and provide a continuous test pattern, for example.
The invention will now be described by way of example with reference to the accompanying drawings in which:
FIG. 1 is a block diagram illustrating one embodiment of the present invention;
FIG. 2 is a logic diagram illustrating control circuitry for use with the arrangement of FIG. 1; and
FIG. 3 is a series of timing dia

REFERENCES:
patent: 4012772 (1977-03-01), Chamgers et al.
patent: 4272787 (1981-06-01), Michael et al.
patent: 4689660 (1987-08-01), Kashigi
patent: 4922329 (1990-05-01), Wilkinson
patent: 5192997 (1993-03-01), Imbert et al.

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