Video signal processor and method for processing a scanning line

Television – Image signal processing circuitry specific to television

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Details

348715, 348721, 348718, 348719, 348555, H04N 514, H04N 964

Patent

active

055551971

ABSTRACT:
A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

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S. Gohshi et al., "Consideration about a Chrominance Signal Processing or MUSE System," ITEJ Technical Report, vol. 16, No. 32, pp. 13-18, ICS '92-40 (Jun., 1992).
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