Television – Synchronization – Automatic phase or frequency control
Reexamination Certificate
2000-10-23
2003-10-14
Miller, John (Department: 2614)
Television
Synchronization
Automatic phase or frequency control
C348S471000, C348S540000, C348S689000, C348S723000, C348S724000, C386S349000, C455S042000
Reexamination Certificate
active
06633340
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a video signal processor for use in a videotape recorder.
A video signal processor, which includes a frequency modulator with automatic frequency control capabilities and is applicable to a videotape recorder, is disclosed in Japanese Laid-Open Publication No. 10-108137. Hereinafter, a video signal processor of this type will be described.
FIG. 13
illustrates a configuration for the known video signal processor. The luminance component of an input video signal (which will be simply called a “luminance signal”) is input to a clamping circuit
11
, which clamps a sync tip level of the luminance signal. Then, the luminance signal is pre-emphasized by a preemphasis circuit
12
and clipped by a white clip and dark clip circuit
13
. Next, a frequency modulator (which will be herein called an “FM modulator”)
14
outputs a frequency-modulated signal (which will be herein called an “FM modulated signal”) of the luminance signal.
On the other hand, a sync separator
81
separates only a sync signal from the luminance signal that has had its sync tip level clamped by the clamping circuit
11
, and then outputs the sync signal to a pulse generator
82
. In an interval other than a vertical blanking interval, the pulse generator
2
generates pulses with a width of 50 &mgr;s synchronously with horizontal-sync pulses, i.e., each pulse generated starts at the leading edge of a horizontal-sync signal.
A counter
83
receives not only the pulses, generated by the pulse generator
82
, as reset pulses, but also the output signal of the FM modulator
14
as clock pulses. And the counter
83
starts counting the number of clock pulses on the leading edge of the horizontal-sync signal. A value “9” is set for the counter
83
. That is to say, when the count of the counter
83
reaches this value, the counter
83
informs another pulse generator
84
of that. Accordingly, the pulse generator
84
generates pulses with a width nine times longer than the period of the FM modulated signal that has been output from the FM modulator
14
.
A crystal oscillator (which will be herein called a “VXO”)
85
outputs a signal to a counter
86
at a frequency twice higher than a sub-carrier frequency fsc. The counter
86
receives not only the pulses, generated by the pulse generator
84
, as reset pulses, but also the output pulses of the VXO
85
as clock pulses. And the counter
86
outputs the count of the input clock pulses to a decoder
87
. The decoder
87
compares a predefined value, which was determined in accordance with the type of the video signal or the method of recording, to the output value of the counter
86
and then outputs a signal representing the equality or inequality of these values.
An error signal generator
88
outputs one of the following two types of error signals to an integrator
50
in accordance with the output of the decoder
87
. Specifically, if the output of the counter
86
is greater than the predefined value of the decoder
87
, then the error signal generator
88
outputs an error signal of the type increasing the frequency of the FM modulated signal output from the FM modulator
14
. Conversely, if the output of the counter
86
is smaller than the predefined value of the decoder
87
, then the error signal generator
88
outputs an error signal of the type decreasing the frequency of the FM modulated signal output from the FM modulator
14
. In response, the integrator
50
integrates the error signal received and then outputs an integrated error signal ei to the FM modulator
14
, which controls the frequency of the FM modulated signal in response to the integrated error signal ei.
FIG. 2
illustrates a configuration for the integrator
50
shown in
FIG. 13. A
potential at the positive electrode of a capacitor
55
is output as the integrated error signal ei to the FM modulator
14
, thereby controlling the frequency of the FM modulated signal. If the error signal generator
88
outputs the error signal of the type increasing the frequency of the FM modulated signal, then a switch
51
turns ON and a current source
53
charges the capacitor
55
. As a result, a potential at the output terminal rises and the frequency of the FM modulated signal increases. Alternatively, if the error signal generator
88
outputs the error signal of the type decreasing the frequency of the FM modulated signal, then a switch
52
turns ON and a current source
54
discharges the capacitor
55
. As a result, a potential at the output terminal falls and the frequency of the FM modulated signal decreases.
However, the integrator
50
shown in
FIG. 2
analogically integrates the error signal, output from the error signal generator
88
, using the capacitor
55
. Accordingly, if extraneous noise has instantaneously entered a horizontal-sync signal for the luminance signal, for example, then the error signal generator
88
will output the error signal and the potential of the integrated error signal ei will change. As a result, the frequency of the FM modulated signal may change, too. In that case, while video is reproduced (i.e., after the modulated signal has been demodulated), the clamping circuit might operate erroneously to generate horizontal striped noise on the screen. To avoid such an unfavorable situation, the capacitance value of the capacitor
55
is increased or the current value of the current sources
53
and
54
is decreased according to the prior art. Such a technique, however, adversely delays the response of the frequency control. In addition, it is impossible to eliminate the potential variation of the integrated error signal ei due to the extraneous noise.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a video signal processor that can reduce the deterioration of image quality resulting from the superposition of extraneous noise on a sync signal of a luminance signal.
An inventive video signal processor includes frequency modulator, frequency discriminator and frequency controller. The frequency modulator outputs-a frequency-modulated signal of a luminance signal input thereto. The frequency discriminator receives a reference frequency signal and the frequency-modulated signal and outputs a first or second error signal every horizontal or vertical scanning interval. Specifically, if a ratio of a frequency of the frequency-modulated signal during a horizontal- or vertical-sync signal interval to a frequency of the reference frequency signal is smaller than a predetermined ratio, the discriminator outputs the first error signal. Alternatively, if the ratio is greater than the predetermined ratio, the discriminator outputs the second error signal. The frequency controller outputs, responsive to the first and second error signals, a control signal to the frequency modulator. Specifically, if the first error signal has been input to the controller a preset number of times or more during an interval before the second error signal is input thereto, the controller instructs the modulator to increase the frequency of the frequency-modulated signal. Alternatively, if the second error signal has been input to the controller a preset number of times or more during an interval before the first error signal is input thereto, the controller instructs the modulator to decrease the frequency of the frequency-modulated signal.
The inventive processor controls and instructs the frequency modulator to change the frequency of the frequency-modulated signal only if the frequency discriminator has output one of the two types of error signals a preset number of times or more before the discriminator outputs the other type of error signal. Accordingly, the frequency of the frequency-modulated signal can be controlled at a target value with the effects of random noise lessened sufficiently.
In one embodiment of the present invention, the frequency controller may include first and second counters, first and second switches and integrator. The first counter receives the first and second error
Ohara Atsushi
Yoneda Takuji
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Miller John
Natnael Paulos
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