Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-08-15
2002-10-08
Chow, Dennis-Doon (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S099000
Reexamination Certificate
active
06462726
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a video signal processing apparatus which converts an analog video signal to a digital signal.
BACKGROUND ART
Recently, a liquid crystal display device is mainly developed as a video apparatus to replace a cathode ray tube (CRT) display therewith. Video signals received from a personal computer by a display device such as a liquid crystal display (LCD) device are analog signals, and the signal level thereof changes in the unit of dot period. Therefore, a sampling clock signal matching to the dot period is needed for signal processing when the signal is written to a memory, when the signal is displayed on a matrix display device, and the like. However, most personal computers do not have an output terminal of such a sampling clock signal. Therefore, it is necessary to reproduce the sampling clock signal based on horizontal synchronization signal or the like received from a computer or the like. Further, the analog video signal cannot be obtained correctly if it is not sampled at a timing in a dot period when a stable signal is outputted. Therefore, the sampling timing has to be appropriate. Then, an appropriate timing of the sampling clock signal is set manually.
In a video apparatus, the sampling clock signal can be reproduced with a phase-locked loop (PLL) circuit by multiplying the input horizontal synchronization signal and by making both frequency and phase match to those of the input signal. However, the output signal of the PLL circuit has a phase delay because the timing signal required for display control is generated in a logic circuit at a later stage. Because this phase delay depends on the frequency of the input signal, it can not determined uniquely in a video apparatus which can receive various input signals. Therefore, scattering of the timing signal due to phase delay is a problem, especially on sampling.
In order to optimize the sampling point, a video information apparatus disclosed in Japanese Patent laid open Publication 9-149291 (1997) uses auto-correlation of video signals between frames. That is, a delay time of sampling clock signal is changed successively, and the auto-correlation between frames of video signals after analog-to-digital conversion is determined for each delay time. Then, a point having low correlation is adopted as a point at which the signal is changed. Then, by changing the sampling clock delay, an optimum sampling point is determined at a midpoint or thereabout of the signal-changing point. However, this conventional optimizing circuit needs a frame memory in order to determine the correlation value. Therefore, a complicated memory control circuit and high-speed clock signal are needed. A method using multiple A/D converter circuits is known as a method not using a memory. However, this method has a problem that a plurality of delay circuits for sampling clock are necessary.
An object of the invention is to provide a video signal processing apparatus which optimizes the sampling point when an analog video signal is converted to a digital signal.
DISCLOSURE OF THE INVENTION
A first video signal processing apparatus according to the present invention comprises:
a clock generator which generates a sampling clock signal for digitizing a video signal based on an input synchronization signal;
a phase controller which controls phase of the sampling clock signal at one of a plurality of phases in one period of the sampling clock signal;
a first signal generator which generates a first signal when the input video signal is larger than a threshold level;
a first counter which counts the first signal received from the first signal generator in a predetermined time;
a second signal generator which generates a second signal when the input video signal is larger than another threshold level, at a timing according to the sampling clock signal controlled by the phase controller;
a second counter which counts the second signal received from the second signal generator in the predetermined time; and
a controller which makes the phase controller sequentially change the phase of the sampling clock signal in a period of the sampling clock signal, repeats the phase change over one or more periods of the sampling clock signal and sets the phase of the optimum sampling clock signal based on a difference between the output signals of the first and second counters obtained for each of the changed phases.
For example, the controller set the optimum phase of the sampling clock signal according to a plurality of the subtraction results obtained by the subtractor which performs subtraction between the output signals of the first and second counters. Thus, the phase of the sampling clock signal can be controlled by using a simple structure that the times of the cases when the video signal exceeds the threshold level is counted by the two counters. Further, timing control of the output signal of the binarizer circuit and that of an analog-to-digital converter are not needed. Further, high speed sampling clock signal is not needed to control the phase of the sampling clock signal, so that consumption power can be decreased. Further, because the sampling clock signal is not needed after the output of the binarizer circuit and the analog-to-digital converter, the counters can process a high speed signal. Therefore, this decreases consumption power and is advantageous for fabricating a large scale integrated circuit thereof.
In the video signal processing circuit, the optimum sampling clock timing can be set in various ways. For example, the controller sets a phase of the sampling clock signal, at which an absolute value of the count values of the first and second signals is equal to or smaller than a predetermined value, to the phase of optimum sampling clock signal. Alternatively, the controller sets a phase of the sampling clock signal, at which an absolute value of the count values of the first and second signals is equal to or smaller than a predetermined value and the absolute value is smallest, to phase of optimum sampling clock signal. Alternatively, the controller makes the phase controller change sequentially the phase of sampling clock signal in a period of the sampling clock signal, and when the controller continuously detects a phase of the sampling clock signal, at which an absolute value of count values of the first and second signals is equal to or smaller than a predetermined value, the controller sets a center value of the continuously detected phases of the sampling clock signal to the phase of optimum sampling clock signal. Alternatively, the controller makes the phase controller change sequentially the phase of sampling clock signal in a period of the sampling clock signal, and when the controller detects two or more phases of the sampling clock signal, at which an absolute value of count values of the first and second signals becomes maximum, the controller sets a center value of the two or more phases of the sampling clock signal to the phase of optimum sampling clock signal.
Further, in the video signal processing circuit, the controller preferably stops to control the phase controller when the output value of the first counter is equal to or smaller than a predetermined value. Thus, the phase control is stopped for video signal which does not change much, so that malfunction is prevented when the optimum sampling point is detected.
Further, in the video signal processing circuit, the controller preferably further comprises a threshold level controller which controls the threshold level of the first signal generator, and a comparator which compares the output signal of the second signal generator with a different threshold level. The controller decides whether the output value of the first counter is equal to or smaller than the predetermined level. Then, it decreases the threshold levels of the first signal generator and of the comparator when the output value of the first counter is equal to or smaller than the predetermined value. The output of the first counter is equal to or smaller than the
Hamada Masanori
Masuda Hiroshi
Chow Dennis-Doon
Matsushita Electric - Industrial Co., Ltd.
Wenderoth , Lind & Ponack, L.L.P.
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