Computer graphics processing and selective visual display system – Plural display systems
Reexamination Certificate
2001-08-06
2003-10-07
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural display systems
C345S204000, C345S213000, C345S001300, C345S002100, C345S003100, C345S903000
Reexamination Certificate
active
06630913
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a video signal processing system for driving multiple monitors, and more particularly, to a video signal processing system for driving multiple monitors, which outputs video signals for driving multiple monitors during one period of clock signal by connecting the monitors with one video card and a single cable and drive the monitors.
BACKGROUND ART
In general, a video card, i.e., a video graphic adapter, which is a device for processing image (character and picture) information of a computer and outputting to a monitor, is a device for controlling color and brightness indicated with luminescent points (pixels or dots) of the monitor. The video card is called a display adapter, a graphic card, a graphic adapter, a video adapter and so on.
The display adapters have similar structures in outward appearance, except a bus type structure. It means that the only standard for sorting VESA (Video Electronic Standard Association), PCI (Peripheral Component Interconnection) and AGP (Accelerated Graphics Port) display adapters is a difference between input/output buses. The display adapter includes a video chip (CRTC), a VRAM (Video RAM), a VGA (Video Graphics Array) BIOS RAM, a feature connector, a VESA feature connector (VAFC: VESA Advanced Feature Connector) a Korean font ROM, a Korean signal processing chip, a video signal output connector, and so on.
For the connector for connecting the display adapter and the monitor, there are 15-pins D type connectors, BNC connectors and USB connectors.
However, the BNC connector cannot send and receive VESA data channel signal, since using five connectors for image signal (R/G/B) and horizontal/vertical sync signal (H/V-sync) Thus, if wanting to connect the BNC cable in Windows 98, a user must designate the kind of the monitor manually since the BNC connector cannot sense the monitor with PnP (Plug & Play) function of Windows 98.
Meanwhile, video image consists of hundreds of scanning lines. The scanning lines are converted into strength of electricity according to the brightness and send image in electric wire or wave. A part, which receives image, cannot know a length of one line or which line is the start of screen.
Therefore, when image signal (R/G/B) is sent, the length of one line and a portion where the screen is started are indicated.
The indication of the length of one line is called horizontal sync signal (H-sync) and the indication of the start of screen is called vertical sync signal (V-sync). Thus, original image can be reconstructed.
Signal output from the video card is sent to three electronic guns disposed at a rear surface of a CRT (Cathode Ray Tube). Each electronic gun emits electronic stream every three colors (R, G and B), and the intensity of stream is controlled with signal output from a video board.
To drive multiple monitors with one computer, the video cards in the same number as the monitors are connected to the computer.
To realize such function, the operation of two monitors is controlled using one video card having a dual monitor function.
However, for this, a video card for dual monitors must be used. The video card for dual monitors has two output ports, and each port must be connected to each monitor through a connection cable.
To drive the multiple monitors using a video card having one output port, the video cards of the same number as the monitors must be used and connected through connector cables.
As shown in
FIG. 1
, the structure of a conventional video card will be described as follows. The conventional video card includes: a clock signal (CLK) supply part
1
for outputting CLK for transmitting video signal; a monitor controlling part
2
for outputting memory access signal (MA) according to the period of CLK provided from the CLK supply part; a memory
3
for outputting data signal according to MA output from the monitor controlling part
2
after receiving MA output from the monitor controlling part
2
and receiving video signal (R/G/B) and H/V-sync; a latch circuit
4
for latching data signal output from the memory
3
and providing to the monitor; and an inverter
5
for inverting CLK output from the CLK supply part
1
and providing to the latch circuit
4
.
FIG. 2
illustrates waveform output of each part. Referring to
FIG. 2
, the operation of a conventional monitor driving signal control circuit will be described. CLK (b point in
FIG. 1 and b
waveform in
FIG. 2
) output from the CLK supply part
1
is applied to the monitor controlling part
2
, and at the same time, CLK (b point in
FIG. 1 and b
waveform in
FIG. 2
) inverted by the inverter
5
is applied to the latch circuit
4
.
Meanwhile, the monitor controlling part
2
provided with CLK provides MA to the memory
3
. The memory
3
outputs separately input R/G/B and H/V-sync into data signal using MA provided from the monitor controlling part
3
. The data signal is output after a little time delay (dT
1
) in comparison with MA.
The data signal output from the memory
3
is applied to the latch circuit
4
and inverted through the inverter
5
. After that, only data signal latched by the latch circuit
4
during one period of CLK is accessed and applied to an output terminal to be displayed on the screen of the monitor.
Through the above process, video signal provided to one monitor during one period of CLK is output.
Because the conventional video signal processing circuit operated like the above outputs only one video signal during one period of CLK, which outputs video signal, only one monitor is connected to one video card.
Therefore, to drive the multiple monitors using the conventional video signal processing circuit, video cards and connection cables of the same number as the monitors must be used, and thus, it is too heavy a burden.
Moreover, even though the dual monitor video card having two output ports is used, the monitors connected to the two video card output ports must be connected through two separate connection cables.
DISCLOSURE OF INVENTION
Therefore, it is an object of the present invention to provide a video signal processing system capable of driving at least two or more monitors with one video card by controlling output signal of the video card having one output port, thereby controlling the monitors with only one connection cable.
To achieve the above object, the present invention provides a video signal processing system f or driving multiple monitors including: a clock signal (CLK) supply part for outputting CLK for transmitting video signal; a monitor controlling part for outputting memory access signal(MA) according to the period of CLK provided from the CLK supply part; a memory for outputting data signal according to MA output from the monitor controlling part after receiving MA output from the monitor controlling part and receiving video signal (R/G/B) and horizontal/vertical sync signal (H/v-sync) from a video card through a single cable; a plurality of latch circuits for latching data signal output from the memory, dividing into multiple data during one period of CLK and outputting the latched data to the monitors; an inverter inverting and outputting CLK output from the CLK supply part; a delay circuit delaying and outputting CLK inverted by the inverter; and a flip-flop circuit for outputting in flip-flop and inputting into the latch circuits after receiving CLK from the delay circuit.
As described above, by dividing and outputting video signal output during one period of CLK into multiple video signals, the system according to the present invention can drive the multiple monitors with only one video card.
The present invention can be changed, converted, replaced and substituted within a range of the business model, technical method and system and is not restricted in the above.
REFERENCES:
patent: 5488385 (1996-01-01), Singhal et al.
patent: 5608418 (1997-03-01), McNally
patent: 5694141 (1997-12-01), Chee
patent: 5949437 (1999-09-01), Clark
patent: 6297817 (2001-10-01), Larson et al.
patent: 6483503 (2002-11-01), Spannaus et al.
Shalwala Bipin
Shapiro Leonid
Tophead.com
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