Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2002-04-05
2004-10-19
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S212000, C345S213000, C345S214000, C345S215000, C345S503000, C345S504000, C382S236000, C382S243000, C386S349000, C386S349000, C386S349000, C348S468000, C348S761000, C348S778000
Reexamination Certificate
active
06806872
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a video signal processing system comprising a display output module for digitally processing a video signal that is controlled by a host CPU.
BACKGROUND OF THE INVENTION
Traditionally, a display output module for handling a digital video signal has been controlled in central processing performed by a host CPU.
When the host CPU updates display setting data, the updated data should be inputted into the display output module during a non-display period. The non-display-period can be identified by using a vertical sync signal.
If display setting data were changed during a display period, then that would be perceived by a user as degradation in image quality or screen flickering, because the display settings are immediately reflected in the display output module. As solutions to this problem, digital signal processing circuit controllers are disclosed in Japanese Patent Laid-Open No. 63-143590 and Japanese Patent No. 2752082.
The technology disclosed in Japanese Patent Laid-Open No. 63-143590 provides the following configuration.
A display output module includes first display setting registers, second display setting registers, a display processing circuit, and an enable bit indicating that the second display setting register is update-enabled. A host CPU negates the enable bit when data is written into the first display setting registers.
Then, changes to display settings are sequentially written into the first display setting registers. After the display settings are written into the first registers, the enable bit is asserted.
When the enable bit is asserted and a vertical sync signal indicates a non-display period, the second display setting register is loaded with an output from the first display setting registers and outputs it to the display processing circuit.
FIGS. 18 and 19
shows a technology disclosed in Japanese Patent No. 2752082.
As shown in
FIG. 18
, a display output module includes flip-flops
323
-
325
, which are first display setting registers, flip-flops
327
-
329
, which are second display setting registers, and a digital video signal processing circuit
326
, which is a display processing circuit. A microcomputer
321
, which is a host CPU, inputs a vertical sync signal to change display settings and updates values in the first display setting registers in one vertical synch signal period.
The inputs of the second display setting registers are connected to the outputs of the first display setting registers. The second display setting registers are loaded with outputs from the first display setting registers in synchronization with the vertical sync signal and output it to the display processing circuit.
The microcomputer
321
and a decoder
322
in
FIG. 18
are interconnected through a bus
330
to send and receive control data and address data to and from each other. The D-flip-flops
323
,
324
, and
325
are connected with the decoder
322
through a data line
331
and receive the control data and receive a selection signal through signal lines
332
A,
332
B, and
332
C.
Symbol “a” in
FIG. 19
indicates the vertical sync signal, “V” indicates a vertical synch signal period, and “1V” indicates a vertical scan period. Symbol “b” indicates an operation of the microprocessor
321
, symbols “c”, “d”, and “e” indicate an operation of the D-flip-flops
323
,
324
, and
325
, respectively, and symbols “f”, “g”, and “h” indicate operations of the D-flip-flops
327
,
328
,
329
, respectively.
Period
341
indicated by “b” in
FIG. 19
is a preparation period. The preparation is for setting control data and address data in a predetermined register of the microcomputer
321
. Period
342
is for monitoring an incoming vertical sync signal and, when the vertical sync signal is detected, obtaining it. Thus, the microcomputer
321
can know the point of the vertical sync signal.
FIG. 19
shows a timing chart, in which symbol “all” indicates control data transferred to D-flip-flop
323
together with address data at address A, “b” indicates control data transferred to D-flip-flop
324
together with address data at address B, and “c” indicates control data transferred to D-flip-flop
325
together with address C. The time chart shows the transfer of data A, a, B, b, and C, c mentioned above.
As described above, display setting data input into the display processing circuit is updated with the timing of a vertical sync signal in either of these control methods for display setting.
However, the above-described prior arts have the following problems.
The first problem is that the host CPU must generate an interrupt to input the vertical sync signal or means such as polling to a flag in which the vertical sync signal is reflected in order for the host CPU to control the generation or modification of display setting data.
In particular, the vertical sync signal is not associated with display setting changes in the display setting control method described in Japanese Patent Laid-Open No. 63-143590. In a video signal processing system that requires frequent display setting changes, there is the likelihood that the host CPU cannot know a display setting change and the next display setting change occurs before the host CPU detects the display setting change and, as a result, a plurality of display setting changes are made in one display period starting with a vertical sync signal and only the last display setting change is reflected on display. To avoid this problem, the host CPU must perform control in synchronization with the vertical sync signal.
The second problem is that the cycle for a change to display setting data must be started by the host CPU in synchronization with the vertical sync signal and the change must be made in a non-display period.
Specifically, an embodiment of the display setting control method is described in Japanese Patent No. 2752082 in which a host CPU inputs the vertical sync signal as an interrupt signal to prepare update data to be placed in the first display setting register and starts a write access to the first display setting register.
As shown at b′ in
FIG. 19
, however, if the vertical sync signal makes a transition during the access by the host CPU for changing the display setting data, a part of display setting data to be changed is not updated before a display period starts, thus the display output module outputs display setting data being updated together with updated display setting data.
While proper display setting data is displayed eventually after a number of vertical sync signal transitions take place and all display setting data is settled, degraded image quality is provided during progress of the update.
To address this problem, a method has been disclosed for dividing the vertical sync signal to prolong a display setting update interval.
However, this control method cannot ensure that display setting changes are made at once in a system in which the amount of display setting data is very large because of diversified digital signal processing, a system in which an application is running under an operating system and display setting register change time is unpredictable from the application due to another task, or a system having an internal configuration in which access from the host CPU to a display setting register is not immediately reflected.
A requirement common to the first and second problems is that the host CPU must monitor a vertical sync signal in controlling display setting. Therefore, the execution of an application software program is interrupted by the vertical sync signal, degrading the performance of the system.
There is another problem that because only a part of display setting data is changed or different display setting data changes are periodically performed and the data must be set by the host CPU in the display module each time a change is made, the number of cycles consumed by a host CPU for controlling a display output module is increased.
DISCLOSURE OF THE INVENTION
It is an object of the present invention to provide a video signa
Masumoto Masayuki
Mino Yoshiteru
Abdulselam Abbas
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P.
Wu Xiao
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