Computer graphics processing and selective visual display system – Display driving control circuitry – Adjusting display pixel size or pixels per given area
Reexamination Certificate
2000-10-18
2003-12-16
Awad, Amr (Department: 2675)
Computer graphics processing and selective visual display system
Display driving control circuitry
Adjusting display pixel size or pixels per given area
C345S699000, C345S213000, C348S556000
Reexamination Certificate
active
06664977
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a video signal processing device in an image display device (e.g., a crystal liquid display, or a plasma display) on which pixels are fixed in number for display and, more specifically, to a video signal processing device subjecting a video signal inputted into the image display device to A/D conversion with two-phase processing.
BACKGROUND ART
In recent years, with the advancement in resolution of a computer as an image signal source, a clock frequency for an image display device has been becoming increasingly faster. In order for the image display device to deal with the faster clock frequency, a digital signal processing device where an incoming A/D-converted video signal is processed is required to operate according to the faster clock. This brings about problems such as higher power consumption in the image display device, and an increase in cost, for example.
To get around such problems, a conventional image display device lowers the clock frequency to half by carrying out two-phase processing in an A/D converter. Thereby, the digital signal processing device provided in a stage subsequent to the A/D converter has no need to operate in accordance with the faster clock. Herein, the processing carried out in the A/D converter may be four-phase or six-phase, and is similarly effective to the two-phase processing.
Herein, as to the A/D converter carrying out the two-phase processing, various types of products are available. For example, these include a CXA3026AQ model (manufactured by SONY), and an AD9054BST model (manufactured by AnalogDevices).
FIG. 17
is a block diagram showing the structure of the conventional video signal processing device carrying out the two-phase processing in the A/D converter. In
FIG. 17
, the video signal processing device is an A/D converter
3
receiving a reference signal
9
and a video signal
24
from an image signal source, carrying out the two-phase processing, and outputting first phase data
10
and second phase data
11
. Described next below is the operation of such video signal processing device with reference to
FIGS. 17 and 18
.
FIG. 18
is a diagram for explaining the operation of the A/D converter
3
in FIG.
17
. In
FIG. 18
, a to e denote video data included in the video signal
24
in a valid video period. Blackened objects in the shape of a circle, diamond, square, and triangle denote data in the pedestal level, specifically black data, in a back porch. Moreover, t
1
to t
10
each indicate a certain time. Arrows therein schematically show the two-phase processing in the A/D converter
3
.
In
FIG. 18
, the video signal
24
includes the back porch and the video data. The back porch is between time t
1
(or before) and time t
5
, while the video signal data is included from time t
5
and onward. Accordingly, the video signal
24
has such structure that a leading edge of a signal including the video data follows an end of the back porch.
Herein, with reference to a pulse of the reference signal
9
provided to the A/D converter
3
, the digital data both outputted from the A/D converter
3
is determined based on a phase relationship between the digital data and the video signal
24
. Generally, the reference signal
9
is a horizontal synchronizing signal provided from the image signal source.
First, as to the first phase data
10
, with reference to the pulse of the reference signal
9
, the A/D converter
3
starts the two-phase processing at time t
1
. As shown in
FIG. 18
, at time t
3
, the black data denoted by the blackened circle is outputted from the A/D Converter
3
as the first phase data
10
. At the same time, the black data denoted by the diamond is outputted from the A/D converter
3
as the second phase data
11
. Thereafter, similarly at time t
5
, the black data each denoted by the square and the triangle is outputted.
Accordingly, in the video signal
24
, when the number of data in the back porch, that is from a leading edge of the pulse of the reference signal
9
to immediately before head data a, is even, the head data a is outputted from the A/D converter
3
as the first phase data
10
. On the other hand, when the number of data in the back porch is odd, the head data a is outputted from the A/D converter
3
as the second phase data
11
.
The problem herein is, if such conventional structure is applied, a display, e.g., a crystal liquid display or a plasma display, on which pixels are fixed in number for display, may be one dot short when displaying the video data. Next, such a problem is described below by referring to FIGS.
19
through
20
(
b
).
FIG. 19
is a schematic diagram for explaining the arrangement of output data and display status on the display for a case where the video data a shown in
FIG. 18
is outputted from the A/D converter as the first phase data. FIG.
20
(
a
) is a schematic diagram for explaining the arrangement of output data and display status on the display for a case where the video data a shown in
FIG. 18
is outputted from the A/D converter as the second phase data. FIG.
20
(
b
) is a schematic diagram for explaining a case where the data arrangement is the same as in FIG.
20
(
a
), but the display status is different therefrom.
In FIGS.
19
through
20
(
b
), a to t denote data included in a video signal, from an image signal source, observed on an arbitrary scan line in a valid video period. Herein, the data inside of a frame in the shape of a square is displayed on the display, while the data outside of the frame is not displayed on the display.
As shown in
FIG. 19
, when the head data (data displayed on the left end on the display) a of the video signal is included in the first phase data
10
outputted from the A/D converter, the display where pixels displayed thereon are fixed in number displays every video data from a to t. On the other hand, as shown in FIGS.
20
(
a
) and (
b
), when the head data a is included in the second phase data
11
, either the video data t on the right end or the video data a on the left end is problematically not displayed on the display. This is because the digital signal processing device in the stage subsequent to the A/D converter
3
carries out processing in a frequency half of a dot clock coming from the image signal source, causing a video phase on the display to change only in pairs of pixels.
As is known from the above, with the conventional video signal processing device, when the head data a is included in the second phase data
11
, the video data is displayed in a state of one dot short as shown in FIG.
20
(
a
) or (
b
). Consequently, as shown in
FIG. 19
, the video data a to t cannot be simultaneously displayed.
Therefore, an object of the present invention is to provide a video signal processing device capable of, even with an A/D converter carrying out the two-phase processing, displaying every pixel on a display even if a head of video data is not in the first phase output data.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a video signal processing device for displaying, on a display, every pixel in a video signal inputted from an image signal source, the device comprising:
a clock delay circuit for receiving a reference signal, and delaying the reference signal by an odd number of clocks for output;
a multiplexer for selecting either the reference signal or an output signal from the clock delay circuit for output;
an A/D converter for converting the video signal into a digital signal for two-phase output as first phase data and second phase data with reference to an output signal from the multiplexer;
a first leading edge detection circuit for detecting a leading edge of a valid video signal region in the first phase data, and outputting a detection signal corresponding thereto;
a second leading edge detection circuit for detecting a leading edge of a valid video signal region in the second phase data, and outputting a detection signal corresponding thereto;
a first back porch detection circuit for detecting a first
Awad Amr
Matsushita Electric - Industrial Co., Ltd.
Wenderoth , Lind & Ponack, L.L.P.
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