Television – Image signal processing circuitry specific to television – Special effects
Patent
1998-03-25
2000-12-12
Hsia, Sherrie
Television
Image signal processing circuitry specific to television
Special effects
348567, H04N 974, H04N 5445
Patent
active
061605905
ABSTRACT:
A video signal processing circuit uses a buffer memory for reducing or expanding video signals in the generation of child images to be displayed within a display window. Image size data, stored in a header within the buffer memory, and a reduced video signal are prevented from representing different image reduction ratios which might otherwise occur when the reduction ratio is changed. At the time of changing the reduction ratio, image size data SIZ are calculated from a write enable signal based on reduction ratio data K, for a one-field period just after the change by an input video clock generator 22. The calculated image size data are written to a header together with a reduced video signal in a field memory 2, and a flag bit SP indicating the change in the reduction ratio is also written to the header for the one-field period just after the change. When data are read from the buffer memory, the flag bit SP is detected by a display video clock generator 23 to mute a video signal output when there is a likelihood of displaying distorted data. On the other hand, writing to the field memory 2 is inhibited for the one-field period just after the change in the image magnification data so that the muting period of the video signal output can be shortened.
REFERENCES:
patent: 5963221 (1999-10-01), Shimizu et al.
patent: 6008854 (1999-12-01), Shimizu
Ota Seiya
Shimizu Yutaka
Hsia Sherrie
Sanyo Electric Co,. Ltd.
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