Video signal processing circuit for monitoring address passing b

Details Video signal processing circuit for monitoring address passing b Video signal processing circuit for monitoring address passing b

1996-10-15

1998-09-01

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345213, 345515, 395821, G06F 1300

Patent

active

058017186

ABSTRACT:
A write clock signal and a write select signal are outputted from an input video clock generator, a read clock signal and a read select signal are outputted from a display video clock generator, either of first and second field memories is selected as the write memory or the read memory in compliance with the signal level of the respective select signal and writing is carried out in the selected write memory once a predetermined time has elapsed following inversion of the write select signal. When reading has commenced from the first and second buffer memory, a match is detected between the signal levels of the write select signal and the read select signal at each field or at each frame and writing and thus reading address passing is predicted.

REFERENCES:
patent: 4945548 (1990-07-01), Iannarone et al.
patent: 5543824 (1996-08-01), Priem et al.

Affiliated with

Also associated with

Rating

Video signal processing circuit for monitoring address passing b does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Video signal processing circuit for monitoring address passing b, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Video signal processing circuit for monitoring address passing b will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-274742