Television – Format conversion
Reexamination Certificate
1999-07-01
2004-03-23
Hsia, Sherrie (Department: 2614)
Television
Format conversion
C348S458000, C348S581000
Reexamination Certificate
active
06710810
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a video signal processing apparatus such as a resolution processing apparatus or the like for artificially enhancing the resolution of video data.
2. Description of Related Art
Currently, multi-scan display devices are predominant in display devices for use with personal computers, as they can support a variety of display modes which may have the resolution of 640 (horizontal direction)×480 (vertical direction) dots; 800×600 dots; 1024×768 dots; or 1600×1200 dots. For displaying video data having the resolution of 800×600 dots on a full screen of such a display device when it is in a mode of displaying, for example, 1600×1200 dots, signal processing is performed to scale up the video data by a factor of two both in the vertical direction and in the horizontal direction to enhance the resolution of the video data to 1600×1200 dots.
A video signal in accordance with a television standard such as the NTSC standard, has a predefined resolution. Therefore, a television receiver for treating video signals of such the television standard supports the resolution corresponding to this video signal. In recent years, however, high definition television receivers have become commercially available for displaying a video image in a higher resolution than that defined in the television standard. Specifically, the high definition television receiver enlarges a video signal in each of the vertical direction and the horizontal direction, by a desired factor in each direction, to artificially enhance the resolution of a video image, thereby allowing the video image displayed in such a higher resolution.
In this way, such high definition television receivers and the aforementioned personal computers have implemented a resolution change for enlarging an incoming video signal (video data) by a factor of n in each of the vertical direction and the horizontal direction to artificially enhance the resolution of the video signal.
FIG. 1
illustrates a resolution processing apparatus for performing the resolution change, as mentioned above, for incoming video data.
Referring specifically to
FIG. 1
, the resolution processing apparatus comprises a sampling frequency conversion unit
1
; a horizontal resolution processing circuit
5
; a vertical resolution processing circuit
6
; and a resolution processing control circuit
15
.
A timing detector circuit
3
in the sampling frequency conversion unit
1
detects a sampling timing of an incoming video data sequence D composed, for example, of series of 8-bit video data, and supplies a line memory
2
with a write signal in response to each detected timing. It should be noted that each of the video data corresponds to each pixel on a display device
14
, later described. The line memory
2
sequentially fetches each video data in the video data sequence D in response to the write signal. The video data sequence D fetched in the line memory
2
as mentioned above is read therefrom in the fetched order in response to a read signal supplied to the line memory
2
from the resolution processing control circuit
15
, later described, and supplied to the horizontal resolution processing circuit
5
as a video data sequence D
C
. The line memory
2
is organized, for example, of FIFO (First In First Out) memories or the like which have a storage capacity for one horizontal scanning line (hereinafter called the “1H”) in the video data, and which can simultaneously and independently execute a write operation and a read operation.
With the configuration as mentioned, the sampling frequency conversion unit
1
converts the sampling frequency of the incoming video data sequence D to a higher sampling frequency which is adapted to the processing rate of the resolution processing apparatus (for the video data sequence D
C
), and supplies the higher sampling frequency to the horizontal resolution processing circuit
5
.
The sampling frequency is converted for the following reason.
For displaying a moving image, an incoming video signal must be displayed without interruption. However, when the video signal is subjected to a variety of resolution enhancement processing, a continuous display of the moving image cannot be maintained occasionally due to the influence of a delay caused by the processing. To solve this problem, the sampling frequency conversion unit
1
is used to increase the sampling frequency of the incoming video data sequence D (corresponding to the video signal) to provide a higher processing rate in the resolution enhancement processing.
The horizontal resolution processing circuit
5
interpolates the video data sequence D
C
having the sampling frequency increased by the sampling frequency conversion unit
1
to generate a video data sequence D
CH
with an enhanced resolution in the horizontal direction, and supplies the vertical resolution processing circuit
6
with the video data sequence D
CH
.
A line memory
7
in the vertical resolution processing circuit
6
delays the video data sequence D
CH
by a time corresponding to 1H of the video data sequence D
CH
to generate a delayed video data sequence DD
CH
which is output therefrom. In this event, the line memory
7
is organized, for example, of FIFO (First In First Out) memories or the like which have a storage capacity for 1H video data in the video data sequence D
CH
.
A mixer circuit
9
is composed of a first multiplier for multiplying the current video data sequence D
CH
by a coefficient K
1
; a second multiplier for multiplying a 1H delayed video data sequence DD
CH
by a coefficient (1−K
1
); and a first adder for adding outputs of the first and second multipliers to generate one line portion of first interpolated image data. Then, the mixer circuit
9
generates a 1H portion of a first video data sequence D
HVI
by the following calculation (1) using the foregoing video data sequence D
CH
, delayed video data sequence DD
CH
, and predetermined coefficient K
1
, and supplies the first video data sequence D
HVI
to a frame memory
11
:
D
HVI
=DD
CH
·K
1
+
DD
CH
(1
−K
1
) (1)
A mixer circuit
10
, which has a similar configuration to that of the mixer circuit
9
, generates a 1H portion of a second video data sequence D
HV2
by the following calculation (2) using the foregoing video data sequence D
CH
and delayed video data sequence DD
CH
, and a predetermined coefficient K
2
, and supplies the second video data sequence D
HV2
to the frame memory
11
:
D
HV2
=D
CH
·K
2
+
DD
CH
(1
−K
2
) (2)
The predetermined coefficients K
1
, K
2
have coefficient values in accordance with the degree to which the resolution is enhanced, and are generated by the resolution processing control circuit
15
.
With the configuration as described, the vertical resolution processing circuit
6
newly generates 2H portions of video data sequences (DH
HV1
, D
HV2
) based on a 1H portion of video data sequence in the video data sequence D
CH
, and a video data sequence 1H before this video data sequence. Thus, a video data sequence having the number of horizontal scanning lines twice as much as the incoming original video data sequence D is generated, thereby enhancing the vertical resolution. It should be noted that each of the predetermined coefficients K
1
, K
2
has a coefficient value in accordance with the degree to which the resolution is enhanced, and is generated by the resolution processing control circuit
15
.
The frame memory
11
alternately stores the first video data sequence D
HV1
and the second video data sequence D
HV2
. Subsequently, the stored image data are sequentially read from the frame memory
11
, and supplied to the display device
14
of a matrix display type such as a plasma display panel, by way of example, as a high definition video data sequence DH. One screen of the display device
14
may be formed of (n·m) pixels in a matrix of n rows and m columns. In this configuration, the number of r
Hoshikawa Masanori
Kida Hiroshi
Hsia Sherrie
Perman & Green LLP
Pioneer Electronic Corporation
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