Television – Synchronization – Sync generation
Reexamination Certificate
1998-06-08
2001-04-17
Eisenzopf, Reinhard (Department: 2714)
Television
Synchronization
Sync generation
C348S524000, C348S536000, C348S571000, C348S572000, C348S607000, C348S497000
Reexamination Certificate
active
06219105
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a video signal processing apparatus for modulating a digitized video signal synchronized with a frame signal supplied from the outside to convert the digitized video signal to an analog video signal which is displayed on a TV set.
BACKGROUND OF THE INVENTION
Recently, a broadcast station and the like increasingly use digital video tape recorders for business purposes which digitize video signals to record and play back. On the other hand, video cameras for personal use which digitize video signals to record are placed on the market now.
In those devices, only significant pixels of a video signal are recorded. So in playing back a video signal, a synchronizing signal, a burst signal and the like are required to be added to the video signal according to a reference signal, such as a synchronizing signal from the inside or the outside.
Japanese Patent Published Application No. Sho 62-82773(1987) discloses a synchronizing signal adjustment circuit which changes timings of synchronizing an internal video signal with a synchronizing signal of an external video signal.
As precise the stability of frequency of a burst signal as that of crystal is required of the synchronizing signal adjustment circuit disclosed, when generating an external synchronizing signal. At the same time, a synchronizing signal to be added to a luminance signal Y must be synchronized with a frame signal supplied from the outside. For this reason, in modulating a chrominance signal, color difference signals Cr and Cb are required to be converted to analog signals before the external synchronizing signal is generated.
However, the synchronizing signal adjustment circuit disclosed requires analog circuits, such as an oscillator, including a crystal and oscillating at the frequency of a color sub-carrier (3.579549 MHz), a multiplier, and an adder. This requirement makes the circuit structure more complicated, and what is more, the stability against changes in temperature characteristics and a power voltage is difficult to be achieved.
In general, digitized video signals, i.e., a luminance signal Y and two kinds of color difference signals Cr and Cb, are sampled with a frequency of 13.5 MHz. For this reason, the video signal and the color sub-carrier easily cause a beat. This often leads to deterioration of characteristics of a video signal.
To cope with the above-described problems, I have proposed, in my prior art Japanese Patent Published Application No. Hei 9-130823(1997), a video signal processing apparatus of which an encoder for generating a luminance signal comprises only digital circuits even when outputting a video signal synchronized with the outside, and which can stably add a synchronizing signal able to synchronize on a monitor to a luminance signal.
The structure of this video signal processing apparatus is shown in FIG.
5
.
FIG. 5
is a block diagram illustrating a structure of a conventional video signal processing apparatus.
The conventional video signal processing apparatus comprises a first input terminal
40
, a second input terminal
41
, a memory
44
, a PLL unit
42
, a write controller
43
, an oscillator
45
, a synchronizing signal generator
47
, a read controller
46
, an encoder
48
, and an output terminal
49
. The first input terminal
40
is supplied with a digitized video signal (hereinafter referred to as “digital video signal”) Sin comprising a luminance signal and two sorts of color difference signals Cr and Cb. The memory
44
temporarily stores the digital video signal Sin input through the first input terminal
40
. The PLL unit
42
generates a clock signal CLK
1
and a frame signal frp synchronizing with a frame signal fsg input through the second input terminal
41
. The write controller
43
generates a control signal CW of writing the digital video signal Sin to the memory
44
according to a frame signal fsg and a clock signal CLK
1
. The oscillator
45
generates a clock signal CLK
2
having crystal precision using a crystal, and outputs the clock signal. The synchronizing signal generator
47
calculates a number of clocks based on the clock signal CLK
2
input within a cycle of the frame signal fsg, and from the result, generates a synchronizing signal CPSYNC to be added to a video signal Senc which is the output of the apparatus. The read controller
46
generates a control signal CR for reading out data from the memory
44
according to the clock signal CLK
2
and the synchronizing signal CPSYNC. The encoder
48
adds the synchronizing signal CPSYNC supplied from the synchronizing signal generator
47
to a luminance signal Y of a digital video signal Sout supplied from the memory
44
, and converts the resulting signal to an analog signal, while modulating two kinds of color difference signals Cr and Cb of the digital video signal Sout using the clock signal CLK
2
to produce a chrominance signal, and converting the chrominance signal to an analog signal. The output terminal
49
is supplied with an output signal of the encoder
48
, i.e., an analog luminance signal and two sorts of analog chrominance signals.
The operation of the conventional video signal processing apparatus will be explained.
The frame signal of around 30 Hz is supplied through the input terminal
41
to the PLL unit
42
. The PLL unit
42
generates the frame signal frp having 50% duty, based on the clock signal CLK
1
synchronizing with the frame signal fsg, and the clock signal CLK
2
.
The write controller
43
generates the control signal CW for the memory
44
according to the frame signal fsg supplied through the input terminal
41
and the clock signal CLK
1
supplied from the PLL unit
42
. According to the generated write control signal CW, the write controller
43
stores the digital video signal Sin, supplied through the input terminal
40
, in the memory
44
.
The oscillator
45
includes a crystal, and outputs the very stable clock signal CLK
2
of 27 MHz of which the frequency deviation is 20 ppm or below, to the read controller
46
.
The synchronizing signal generator
47
measures the period of a cycle of the frame signal fsg using the clock signal CLK
2
from the oscillator
45
. To be specific, an internal counter is reset at a rising edge of the frame signal fsg, and counts up at a rising edge of the clock signal CLK
2
. The value of the counter is stored in a register at a next rising edge of the frame signal fsg. The number of clocks within a line is defined by the integer part of the value resulting from dividing the number of lines contained in a cycle of the frame signal fsg by the number of counts held in the register, while the remainder defines the skew. Afterwards, the synchronizing signal generator
47
generates the synchronizing signal CPSYNC according to the number of clocks in a line and the clock signal CLK
2
from the oscillator
45
.
The read controller
46
generates the control signal CR for reading the data stored in the memory
44
according to the synchronizing signal CPSYNC generated in the synchronizing signal generator
47
and the clock signal CLK
2
supplied from the oscillator
45
. The digital video signal Sout is read out from the memory
44
according to the control signal CR generated.
The digital video signal Sout has the same sequence of data as the video signal Senc. The timing of reading the digital video signal Sout is adjusted. That is, the jitter between the frame signals fsg and frp is absorbed by the memory
44
.
The digital video signal Sout read out from the memory
44
is supplied to the encoder
48
. The encoder
48
adds the synchronizing signal CPSYNC to the luminance signal Y of the digital video signal Sout, and converts the result to an analog signal, while modulating two kinds of color difference signals Cr and Cb of the digital video signal Sout using the clock signal CLK
2
to produce a chrominance signal, and converting the chrominance signal to an analog signal. The output signal of the encoder
48
is supplied to the output terminal
49
.
In the foregoing convent
Fujii Shozo
Kashiro Takao
Uro Katuji
Desir Jean W.
Eisenzopf Reinhard
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P
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