Television – Image signal processing circuitry specific to television – Special effects
Reexamination Certificate
1998-03-16
2002-06-18
Lee, Michael H. (Department: 2614)
Television
Image signal processing circuitry specific to television
Special effects
C348S567000, C345S668000, C345S671000, C382S298000
Reexamination Certificate
active
06407778
ABSTRACT:
This application claims the priority of Japanese Patent Application No. Hei 9-81470, filed Mar. 31, 1997, which is incorporated herein by reference in its entirety.
BACKGROUND
The invention relates generally to video signal processing.
In the television industry, the Picture In Picture (“PIP”) function is a well-known function used to display multiple pictures on a screen or window. Future multimedia applications, however, demand additional display functions. For example, performing a window display function at an arbitrary reduction ratio, as widely developed in the operating environment of the personal computer, is demanded in the television industry as well. To display other pictures on the window, a buffer memory such as a field memory or a frame memory for synchronizing the picture and the picture is required.
As shown in the reduced video signal processing circuit of
FIG. 1
, an input video signal of a picture is entered into an input processor. The picture is reduced according to reduction ratio data K by using an internal filter circuit
10
so that the reduced video signal is transmitted to field memories
2
,
3
. A control block
4
includes an input video clock generator
5
for controlling performance of a write function to the field memories
2
,
3
, and a display video clock generator
6
for controlling performance of a read function from the field memories
2
,
3
. The reduction ratio data K is fed from an external source to the input video clock generator
5
, from which they are entered into the input processor
1
.
The input video clock generator
5
receives a horizontal synchronizing signal (“H input”) and a vertical synchronizing signal (“V input”) of the input video signal and generates a write clock signal, WCLK, having the same rate as that of a pixel clock synchronized with the H input. The input video clock generator
5
also generates write enable signals, WE
1
and WE
2
, for enabling the field memories
2
,
3
alternately at the field unit for an effective display period of the input video signal. Additionally, the input video clock generator
5
generates a write reset signal, WRST, for resetting the write addresses of the field memories
2
,
3
at the rise of the write enable signals. The field memories
2
,
3
are equipped individually with address counters for designating the write and read addresses independently. The writing address counter is reset by the signal WRST and increments the write addresses by counting the write clock signals WCLK while the enable signals WE
1
and WE
2
are at a high level. The reduced video signal from the input processor
1
then is written in the field memories
2
,
3
.
When the value of the reduction ratio data K is at 1, in other words, when there is no reduction, the write enable signals WE
1
and WE
2
are kept at the high level for the effective video period. When the reduction ratio data K is lower than 1, the reduction ratio data K is used to control when the enable signals WE
1
and WE
2
are high. If, for example, the value of the reduction ratio data K is ½, the high level and the low level are repeated at alternating pixels, as shown at FIG.
2
(
b
) and FIG.
2
(
c
).
The input video clock generator
5
calculates image size data SIZ on the basis of the reduction ratio data K and transmits the data SIZ to the display video clock generator
6
. If the number of horizontal pixels and the number of vertical pixels from the input video signal are 640 and 480, respectively, and if the reduction ratio data K is ½, the image size data SIZ are 320 and 240 for the horizontal SIZ(H) and the vertical SIZ(V), respectively.
To read the reduced video signals from the field memories
2
,
3
, the display video clock generator
6
receives both the horizontal synchronizing signal (“H display”) and the vertical synchronizing signal (“V display”) from the display video signals. Alternatively, the display video clock generator
6
can receive the picture and the display position data (X, Y) indicating the window display position of the reduced image. The display video clock generator
6
generates a read clock signal RCLK at the same rate as that of the pixel clock synchronized with the H display. The display video clock generator
6
also generates read enable signals RE
1
and RE
2
enabling the field memories
2
,
3
alternately at the unit of field for the effective display period of the display video signals. Additionally, the display video clock generator
6
generates a read reset signal RRST for resetting the read addresses of the field memories
2
,
3
at the rise of the read enable signals. The reading address counters in the field memories
2
,
3
are reset by the signal RRST and increment the read addresses by counting the read clocks RCLK while the enable signals RE
1
and RE
2
are at the high level. The reduced video signals then are read from the field memories
2
,
3
.
The H display and the V display may be generated, if known in advance, by the display video clock generator
6
so that the various signals RRST, RCLK, RE
1
and RE
2
can be generated on the basis thereof.
As indicated by
FIG. 4
, the display position data (X, Y) indicates the display position of the picture (of the display video signal), and the image size data SIZ(H), SIZ(V) indicates the size of the picture (of the input video signals) to be displayed on the window. Based on the image size data SIZ(H), SIZ(V) and the image position data (X, Y), the display video clock generator
6
sets the read enable signals RE
1
, RE
2
to the high level only for the effective display period so that the display of
FIG. 4
can be realized (see FIG.
2
(
e
) and FIG.
2
(
f
)). In contrast to the input side, the high level signals are generated continuously.
The image size data SIZ(V), SIZ(H) and the image position data (X, Y) are transmitted from the display video clock generator
6
to a display processor
7
located downstream of the field memories
2
,
3
. The display processing for the window display, such as the framing of the reduced video signals or the addition of background data, is performed by the display processor
7
, and the result is provided as display video signals.
To change the reduction ratio arbitrarily, the processing content has to be changed at both the write side and the read side according to the reduction ratio data. However, the displayed image is disturbed if the processing content is changed during performance of the writing and reading functions. To prevent this disturbance, the change in the reduction ratio is performed during a vertical blanking interval.
There is a delay with respect to the change in the reduction ratio between the write side and the read side because the V input and the V display are not synchronized. If new reduction ratio data K is entered at a time T
1
when the phase of the V display is delayed from the V input (see FIG.
2
(
f
)), the reduction ratio data K is changed at the input video clock generator
5
and the input processor
1
during a vertical blanking interval NP
1
, after T
1
(see FIG.
2
(
a
)). The subsequent display reduction and the write control are performed according to the changed reduction ratio. In the display video clock generator
6
and the display processor
7
, however, the reduction ratio is changed during a vertical blanking interval DP
1
, after T
1
(see FIG.
2
(
d
)). The interval DP
1
occurs after the interval NP
1
so that the video signals, as written according to the changed reduction ratio, are subjected to the display processing during and after the interval DP
1
.
If, however, the new reduction ratio data K is entered at a time T
2
after the vertical blanking interval NP
1
at the V input but before the vertical blanking interval DP
1
at the V display (see FIG.
3
), the reduction ratio is changed in the input video clock generator
5
and the input processor
1
during a vertical blanking interval NP
2
, after T
2
(see FIG.
3
(
a
)). In the display video clock generator
6
and the display processor
7
, however, th
Ota Seiya
Shimizu Yutaka
Fish & Richardson P.C.
Lee Michael H.
Sanyo Electric Co,. Ltd.
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