Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1999-12-03
2003-01-21
Kelley, Chris (Department: 2713)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C348S515000
Reexamination Certificate
active
06510179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a video signal encoding device, and more particularly to a video signal encoding device which rearranges the order of a plurality of input video signals before encoding these signals, just like the MPEG (Moving Picture Experts Group) method.
2. Description of the Related Art
The most popular encoding method currently being employed in the field of digital broadcasting or communications is the MPEG method. The principal encoding tools for this MPEG method are the motion compensation prediction and the DCT (Discrete Cosine Transform), and the video input signals are normally encoded after rearranging the order of the frames thereof in order to effectuate this motion compensation prediction.
FIG. 11
is a schematic diagram showing the general configuration of a conventional video signal encoding device designed for use with the MPEG method which is presented as a frame conversion circuit or the like in the Japanese Patent Application Laid-Open No. 2-58440. In the figure, reference numeral
3
denotes a video signal rearranging circuit, numeral
4
denotes a video signal encoding circuit,
5
denotes a video signal write control circuit,
6
denotes a video signal read control circuit, and
1
a
to
1
c
denote input terminals for the video signal encoding device, whereas numeral
2
a
denotes an output terminal therefore.
In the above configuration, a video input signal
201
input through the input terminal
1
a
is first fed to the video signal rearranging circuit
3
. Further, a video input clock signal
204
input through the input terminal
1
b
and a video input frame pulse
205
input through the input terminal
1
c
are both fed to the video signal write control circuit
5
and the video signal read control circuit
6
. The write control signal
206
as an output of the video signal write control circuit
5
and the read control signal
207
as an output of the video signal read control circuit
6
are fed to the video signal rearranging circuit
3
. In the video signal rearranging circuit
3
, under the control of reading and writing operations of the video input signal
201
on the basis of the write control signal
206
from the write control circuit
5
and the read control signal
207
from the read control circuit
6
, picture frames (or just “frames” hereinafter) of the input signal
201
are rearranged therein so as to output the video signal
202
, and as a result, the thus rearranged frames of the video signal
202
in the video signal rearranging circuit
3
are then encoded in the video signal encoding circuit
4
, and are thereafter output from the output terminal
2
a
as a video encoded data
203
.
FIGS. 12A and 12B
are exemplary views showing an example of the rearrangement of the frames of video signal carried out in the video signal encoding device having the above configuration.
In
FIG. 12A
, the row of numbers
0
,
1
,
2
,
3
, . . . indicates the order of the frames of the video signal which are to be input to the video signal rearranging circuit
3
, whereas the other row
2
,
0
,
1
,
5
. . . shown in
FIG. 7B
indicates the order of the frames rearranged in the video signal rearranging circuit
3
, whereby it is shown that the output order of the frames from the video signal rearranging circuit
3
is different from the input order thereof.
Note that the video signal encoding operation carried out in the video signal encoding device is executed normally on the assumption that video signals each having a correct format are successively input.
However, some of the video signals actually input to the video signal encoding device have not correct signal format, as they are fed to a switching circuit or the like before being input to the encoding device.
FIG. 13
shows an example of the horizontal synchronizing signal of an incorrect video signal format. In this figure, there are shown video input frame pulses
205
as one type of the horizontal synchronizing signals of a video signal format, wherein since the video signal
101
and the video input frame pulse
205
as the horizontal synchronizing signal are not switched exactly at the same timing when they pass through a switching circuit or the like, the time interval of each of the video input frame pulses
205
becomes faulty during the synchronizing operation, as can be observed from the figure that the time interval T is converted to T′ for example, so that the period for each frame becomes inconsistent.
For this reason, since in the conventional video signal encoding device, it is based on the assumption that the video signals of a correct format are successively input thereto, when a video signal is input in an incorrect format, there has been caused such a problem that a video signal of an incorrect picture content is supplied to the video signal encoding circuit
4
, or that a proper encoding processing cannot be conducted with a synchronizing signal of an incorrect video signal format.
SUMMARY OF THE INVENTION
The present invention has been proposed to solve the problems aforementioned, and it is an object of the present invention to provide a video signal encoding device, which is capable of performing correct encoding operation one after another, even if a video signal of an incorrect format is input thereto.
In order to achieve the above object, a video signal encoding device according to the first aspect of the present invention comprises: a video signal rearranging means for rearranging the frame order of video input signals; an encoding frame pulse generating means for generating an encoding frame pulse on the basis of a video input frame pulse and a video input clock signal; a video signal write control means for controlling the write operation of the video signals to the video signal rearranging means on the basis of the video input frame pulse and the video input clock signal, and a video signal read control means for controlling the read operation of the video signals in the video signal rearranging means on the basis of an encoding frame pulse generated by the encoding frame pulse generating means and the video input clock signal.
A video signal encoding device according to the second aspect of the present invention further comprises: an input frame width detection means, which detects a period of one frame (hereinafter may be referred to as “time width of a frame” or just as “frame width”) of a video input signal in accordance with the video input clock signal, and outputs the detected result to the video signal read control means, wherein the video signal read control means compares the detected result with a predetermined value or a video input signal of a correct frame format which was previously input, and controls the video signal rearranging means to read a video signal of another frame instead of a video signal of the corresponding frame which was to be read out otherwise, if the input frame width detection means judges that the video signal is not correct.
A video signal encoding device according to another aspect of the present invention is arranged such that the encoding frame pulse generating means generates the encoding frame pulse first by setting a reference phase in accordance with the video input frame pulse, and thereafter dividing the clock frequency of the video input clock signal by a preliminarily stored predetermined number.
A video signal encoding device according to further aspect of the present invention further comprises: an input/output frame phase difference detection means for detecting a phase difference between the video input frame pulse and the encoding frame pulse from the encoding frame pulse generating means, wherein the video signal read control means controls the video signal rearranging means in such a manner as to read out the video signal of a frame other than the video signal of the corresponding frame that was to be read otherwise, when the phase difference detected by the input/output frame phase difference detection means exceeds a prede
Asano Kenichi
Kasezawa Tadashi
Kazayama Masahiro
Birch Stewart Kolasch & Birch, LLP.
Kelley Chris
Parsons Charles
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