Video signal delay circuit

Details Video signal delay circuit Video signal delay circuit

1985-02-26

1987-01-06

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358213, 365 45, H04N 514, G11C 2702

Patent

active

046351167

ABSTRACT:
A video signal delay circuit comprises an input horizontal transfer register supplied serially with an input composite video signal, an input vertical transfer gate, a plurality of columns of vertical transfer registers, an output vertical transfer gate, an output horizontal transfer register, a horizontal transfer clock pulse generating circuit, a vertical transfer clock pulse generating circuit and a vertical transfer gate pulse generating circuit. The vertical transfer clock pulse generating circuit generates a vertical transfer clock pulse at a rate of once per one horizontal scanning period of the input composite video signal and additionally generates one or more vertical transfer clock pulses during a specific time period. Or, the horizontal transfer clock pulse generating circuit generates a horizontal transfer clock pulse having a selected phase or a selected number of horizontal transfer clock pulses.

REFERENCES:
patent: 4297728 (1981-10-01), Lowe
patent: 4314275 (1982-02-01), Chapman
patent: 4536795 (1985-08-01), Hirota et al.

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