Television – Format conversion – Changing number of lines for standard conversion
Reexamination Certificate
1997-07-11
2001-04-03
Lee, Michael (Department: 2614)
Television
Format conversion
Changing number of lines for standard conversion
C348S536000, C348S554000, C348S706000, C348S556000
Reexamination Certificate
active
06211918
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of video signal processing and, more particularly, to a video signal converter which converts a signal from personal computers to a television signal.
BACKGROUND OF THE INVENTION
As personal computers (hereafter referred to as PCs) become increasingly popular, there is growing demand for the display of PC signals on larger screens using inexpensive means. In general, multi-scan displays and other exclusive displays are used as video display monitors for displaying PC signals. However, large multi-scan displays and other exclusive displays cost a great deal more because of the advanced technology used in these displays.
On the other hand, high definition television sets (hereafter referred to as HDTVs), which are capable of displaying PC signals, are rapidly penetrating the market. Consequently, demands for displaying PC signals on HDTVs are sharply increasing. However, HDTVs are unable to display PC signals directly. An interface is required to link a PC with an HDTV for displaying PC signals on HDTVs. For example, a video signal converter as disclosed in Japanese Laid-open Patent H8-9343 is required. With the use of this video signal converter, PC signals can be displayed on HDTVs. The video signal converter of the prior art is explained with reference to FIG.
5
.
FIG. 5
is a block diagram of the video signal converter of the prior art.
In
FIG. 5
, an input signal processor
51
converts the analog input signal to a digital signal, and separates and outputs the horizontal synchronizing signal (HD
1
) and vertical synchronizing signal (VD
1
) of the input signal. The input signal processor
51
also produces a clock pulse (CK
1
) which is used for converting the input signal to a digital signal.
A compressor
52
condenses the number of picture elements in horizontal and vertical directions in a specified ratio as required, and passes through the signal unmodified when compression is not necessary. A memory
53
provisionally stores data. An expander
54
enlarges the number of picture elements in the horizontal and vertical directions in a specified ratio as required, and passes through the signal unmodified when expansion is not necessary.
An output signal processor
55
conducts necessary signal processing including conversion of the digital signal to an analog signal. A controller
56
outputs a compression or expansion ratio for the horizontal or vertical direction for converting and outputting the input signal in a required form of signal. The required form of the signal is the display format for displaying the signal. The controller
56
also outputs a signal for controlling write and readout of the memory
53
. An output HD
2
/VD
2
/CK
2
generator
57
produces and outputs the output horizontal synchronizing signal (HD
2
) and output vertical synchronizing signal (VD
2
) after conversion. The output HD
2
/VD
2
/CK
2
generator
57
also outputs a clock pulse CK
2
.
The operation of the video signal converter of the prior art configured as illustrated in
FIG. 5
is described below. In order to convert the input signal to a different format, the video signal converter compresses or expands the input signal and then outputs a synchronizing signal in a required form. The video signal converter in
FIG. 5
compresses the input signal using the compressor
52
and expands a signal from the memory
53
using the expander
54
. Both compression and expansion is performed during digital signal processing.
For example, assume the input signals are of the NTSC system, extended definition television standard (hereafter referred to as EDTV standard), high definition television standard (hereafter referred to as HDTV standard), or PC signals of video graphics array (hereafter referred to as VGA specification). Further, it is assumed that the input signals after conversion are also of the NTSC system, EDTV standard, HDTV standard, or PC signals of VGA specification. Compression and expansion of these signals are determined based on the correlation of the input and output signals. When compression is necessary, the video signal converter of the prior art compresses the signal using the compressor
52
and provisionally stores it in the memory
53
. Data are then read out from the memory
53
synchronized with CK
2
and are passed through the expander
53
without undergoing expansion processing. When expansion is necessary, the video signal converter of the prior art passes the signal through the compressor
52
without undergoing compression processing, and provisionally stores it in the memory
53
. Data are then readout from the memory
53
synchronized with CK
2
and are expanded by the expander
53
. If the input signal is the PC signal of VGA specification, for example, and the form of signal required after conversion is the HDTV signal, the vertical frequency of the input signal is 60 Hz and that of the output signal is 59.94 Hz. The difference in the vertical frequency between the input and output signals is converted by controlling write and readout of the memory
53
.
As described above, the video signal converter of the prior art conducts all compression and expansion processes during digital signal processing. Therefore, in order to compress and expand the input signal without any deterioration, it is necessary to provide a sufficient number of taps in compression and expansion filters so that signals are regenerated without distortion due to conversion of the sampling frequency. To satisfy this requirement, a very large-scale circuit is necessary. Moreover, if the input signal is the PC signal of VGA specification and the signal required after conversion is the HDTV signal, the vertical frequency of the input signal is 60 Hz and the vertical frequency of the output signal is 59.94 Hz. To convert between these two frequencies the video signal converter of the prior art uses a large-scale digital circuit for interpolation or the control of write and readout of the memory
53
. Consequently, deterioration in picture quality due to interpolation or missing images may occur.
SUMMARY OF THE INVENTION
The present invention converts an analog video signal to a digital signal using a first clock pulse synchronized to the horizontal synchronizing signal and stores the digital signal in a memory. A second clock pulse synchronized to the vertical synchronizing signal of the input signal is employed for reading out the video signal stored in the memory. The video signal is read out from the memory within a period controlled by a controller. The digital signal retrieved from the memory is reconverted to an analog signal. The controller may prohibit reading out the signal from the memory. During this time a blank signal not including the video signal is output as an analog signal. Thus, the PC output signal is converted from an analog to digital signal, and the digital data is stored in the memory. The digital data is read out using the second clock pulse and a blank signal is output during intervals when the PC output signals have been completely read out from the memory. In this way, the signal can be converted to a required signal standard, a format suitable for display on a selected display device. HDTVs which display video images are capable of displaying the vertical synchronizing signal of a PC signal input. Thus, the video signal converter of the present invention enables the display of a PC signal on an HDTV as a high picture quality.
REFERENCES:
patent: 4831441 (1989-05-01), Ando
patent: 5455628 (1995-10-01), Bishop
patent: 5504532 (1996-04-01), Rhodes
patent: 5673086 (1997-09-01), Fukuoka et al.
patent: 5978041 (1999-11-01), Masuda et al.
patent: 02050596 (1990-02-01), None
patent: 07059054 (1995-03-01), None
patent: 0705034 (1996-04-01), None
patent: 8-9343 (1996-01-01), None
European Search Report, application no. EP97111854 dated Sep. 24, 1998.
Miyata Minoru
Uwabata Hideyo
Lee Michael
Matsushita Electric - Industrial Co., Ltd.
Ratner & Prestia
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