Static information storage and retrieval – Addressing – Sequential
Patent
1985-01-22
1987-03-03
Popek, Joseph A.
Static information storage and retrieval
Addressing
Sequential
365189, 365195, G11C 800
Patent
active
046480773
ABSTRACT:
A semiconductor memory circuit includes memory arrays (10), (12), (14) and (16). Each of the memory arrays has associated therewith shift registers (34), (36), (38) and (40). Transfer gates (54) are disposed between the memory arrays and the associated shift registers. A control circuit (69) is provided for receiving an external transfer signal and transferring the data between the arrays and the associated shift registers. The shift registers are clocked in response to receiving an external shift clock signal to serially output data therefrom. A delay circuit (292) is provided for delaying shifting of data for a predetermined duration to ensure that a complete transfer of data has been effected. Transfer of data is inhibited until the occurrence of the XBOOT signal by circuit (296) to provide for early occurrence of the transfer signal. Data access is maintained by a delay circuit (330) to accommodate late occurrence of the transfer signal by delaying the internal row address strobe.
REFERENCES:
patent: 3930239 (1975-12-01), Salters et al.
patent: 4322635 (1982-03-01), Redwine
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4347587 (1982-08-01), Rao
patent: 4541075 (1985-09-01), Dill et al.
Guttag Karl M.
Pinkham Raymond
Valente Fredrick A.
Vanaken Jerry R.
Anderson Rodney M.
Graham John G.
Popek Joseph A.
Texas Instruments Incorporated
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