Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
1999-04-26
2001-05-22
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C375S240000
Reexamination Certificate
active
06236345
ABSTRACT:
The invention relates to a D/A converter according to the preamble of claim
1
.
The invention further relates to a method for converting a digital input signal into an analogue output signal according to the preamble of claim
4
.
A lot of D/A converters for audio signals are known. There are two basic techniques used in digital-to-analogue converters (D/A converters). These are the so called sigma-delta technique and the resistive or capacitive divider techniques. The sigma-delta technique is attractive because it achieves high resolution by precise timing instead of precisely-matched on-chip components such as resistors. In addition, the expertise needed to produce thin film, laser-trimmed analogue components is difficult to obtain; whereas, high-speed digital switching capability is commonplace in the semiconductor industry.
A basic sigma-delta D/A converter receives a digital input signal which is summed with inverse feedback of the output signal to provide an error signal. The error signal is then processed through an integrator and a comparator to provide the so called bit-stream output signal. This signal conversion technique of using time resolution instead of amplitude resolution matches very well with present CMOS technology with its reduction of power supply voltage and the increase of the intrinsic speed of the transistors. The sigma-delta D/A converter is able to shape the quantisation noise out of the signal band, and any noise beyond that range is filtered out by the subsequent analogue filter in an ideal implementation.
Sigma-delta modulators often require oversampled signals which can be provided by an interpolator. The D/A converter's input signals may be at the so called Nyquist rate or may require interpolation to a higher rate before being provided to the sigma-delta modulator. The sigma-delta modulator is clocked using a high-speed digital clock, which may be different from the D/A converter's input clock.
Such a D/A converter is known from the U.S. Pat. No. 5,585,802.
This known D/A converter comprises a sigma delta modulator as a so called noise shaper followed by filter means.
Such D/A converters are intensively used in voice band and audio band applications but are hardly used in large bandwidth applications such as in the video domain.
Disadvantages of the known D/A converters are that to use these D/A converters for full bandwidth video signals operation frequencies beyond 200 MHz are necessary. Such very high speed circuits are difficult to accomplish. Further this very high speed circuitry dissipates (too) much power.
Another disadvantage is that the filter means used in the known D/A converters requires a large number of so called taps (multiplication's).
SUMMARY OF THE INVENTION
So these known D/A converters are not suitable for video signals.
An object of the invention is to overcome the disadvantages of the prior art, to provide a D/A conversion suitable for full bandwidth video signals.
To this end a first aspect of the invention provides a D/A converter as claimed in claim
1
. A second aspect of the invention provides a method as claimed in claim
4
.
By reducing the sample rate of the sigma delta modulator this D/A converter is able to handle full bandwidth video signals without needing clockfrequencies beyond 200 MHz.
An embodiment of a D/A converter according to the invention comprises the features of claim
2
.
Instead of using a normally used parallel to serial converter (which requires a 216 MHz clock) the D/A converter according to the invention employs a polyphase post processing combined with an (for example on chip) filtering.
By using a polyphase filtering the clock frequency can be reduced.
An embodiment of a D/A converter according to the invention comprises the features of claim
3
.
By using a delay locked loop (DLL) the clock frequency of the polyphase FIR filter means can be easily obtained from the clock frequency of the reduced rate sample rate sigma delta modulator.
REFERENCES:
patent: 4782324 (1988-11-01), Underwood
patent: 5283578 (1994-02-01), Ribner et al.
patent: 5323157 (1994-06-01), Ledzius et al.
patent: 5579004 (1996-11-01), Linz
patent: 5585802 (1996-12-01), Cabler et al.
Dagnachew Birru M.
Roza Engel
U.S. Philips Corporation
Wamsley Patrick
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