Video RAM architecture incorporating hardware decompression

Details Video RAM architecture incorporating hardware decompression Video RAM architecture incorporating hardware decompression

1991-07-22

1993-11-09

Shaw, Dale M.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395166, 395162, 36518901, 36518912, 345191, 345186, G06F 1520

Patent

active

052610497

ABSTRACT:
An image buffer semiconductor chip is described that includes circuitry for decompressing, compressed pixel image data such data comprising at least a pair of color codes and a bit mask including bit positions with values that define which pixels in a pixel subset of the pixel image receive the encoded color code data. The chip comprises a matrix of memory modules with the pixels in a pixel subset stored in an interleaved fashion, one pixel per module. A data bus communicates with all of the memory modules and broadcasts the color codes. A mask register stores the bit mask when it appears on the data bus. Circuitry selectively writes a first color code in the modules in accordance with bit values of a first kind in the MASK and writes the second color code into the modules in accordance with bit values of a second kind in the MASK.

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