Video processing technique using multi-buffer video memory

Details Video processing technique using multi-buffer video memory Video processing technique using multi-buffer video memory

1996-09-03

1998-06-16

Wu, Xiao

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345516, 345508, G09G 500

Patent

active

057678634

ABSTRACT:
In a preferred embodiment, when full-motion video data is to be captured on a hard disk, a full-motion video memory on a video controller card has its addresses segmented into four groups, where each group can store one scaled-down frame (or field) of video data. The video memory is arranged to effectively act as a four-frame, first-in first-out (FIFO) buffer. The holding time of a single frame of data (i.e., four times the conventional holding time) in the video memory is sufficient to allow for the unpredictable variations in the hard drive timing so that frames are not arbitrarily dropped by worst case timing/accessing times of the hard drive. Hence, the average bandwidth and timing of the hard drive, rather than the instantaneous worst case bandwidth and timing of the hard drive, is used when designing the system. Additionally, video data may be read from and written into the same frame area in the video memory as long as the read (capture) and write (video-in) pointers have been determined to not overlap while accessing the same frame area. This more efficiently utilizes the capabilities of the hard drive.

REFERENCES:
patent: 4468708 (1984-08-01), Coleman, Jr.
patent: 4523227 (1985-06-01), Hurst
patent: 4816815 (1989-03-01), Yoshiba
patent: 4862269 (1989-08-01), Sonoda et al.

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