Television – Image signal processing circuitry specific to television – With details of static storage device
Reexamination Certificate
2001-07-12
2004-09-14
Kostak, Victor R. (Department: 2611)
Television
Image signal processing circuitry specific to television
With details of static storage device
C348S716000
Reexamination Certificate
active
06791625
ABSTRACT:
TECHNICAL FIELD
The present invention belongs to a technical field of a video processing for performing an encoding/decoding processing for video data by a processor which can be controlled by a program and the like, and relates to a video processing method and a video processing apparatus which include an address generating apparatus for generating an address for accessing a memory at transmitting data between more than two memories and which can perform an address control so as to access a video data of an effective video data region at accessing video data existing at outside the region of the effective video data stored in the memory.
BACKGROUND ART
In recent years, there is a growing concern about a system such as a visual telephone or a television conference, which system utilizes the video communication. However, since the transmission rate of the communication line employed in this system is generally low, a video encoding/encoding technique is necessary for transmitting a tremendous amount of video data and, actually, various kinds of encoding/decoding systems have so far been proposed. Further, under these circumstance, it is desired a video processing apparatus which performs video encoding/decoding processing by a processor controllable by a program and which can cope with various encoding/decoding systems flexibly by changing the program performing the control. Hereinafter, a conventional video processing apparatus which performs encoding/decoding processing by a processor controllable by a program will be described with reference to FIG.
13
.
FIG. 13
is a block diagram illustrating a construction of a conventional video processing apparatus. This video processing apparatus includes, as shown in
FIG. 13
, a video input/output unit
1300
which inputs/outputs an input video or a display video, an external memory
1302
which memorizes video data or coded data, a processor unit
1303
which is operated by a program control, a DMA bus
1301
which performs the data transmission, in other words, the direct memory access (Direct Memory Access, hereinafter, referred to as “DMA”) between the video input/output unit
1300
or the processor unit
1303
and the external memory
1302
, and a DMA control unit
1305
which controls the data transmission between the video input/output unit
1300
or the processor unit
1303
and the external memory
1302
.
The processor unit
1303
comprises an encoding/decoding unit
1304
which encodes/decodes video data stored in the external memory
1302
.
The DMA control unit
1302
comprises a DMA setting holding unit
1306
which stores the setting information required for generating an access address to the external memory
1302
, a two dimensional address generating unit
1307
which generates an access address of the external memory
1302
in accordance with the setting information of the DMA setting holding unit
1306
, and a DRAM control unit
1308
which controls reading or writing from/to the access address of the external memory
1302
, which access address is generated from the two dimensional address generating unit
1307
.
The video processing apparatus thus constructed, will be described in brief with reference to FIG.
13
and
FIG. 14
particularly on the operation thereof.
At first, when an input video is input to the video input/output unit
1300
, the input video is subjected to the resolution conversion into the video size as a target of encoding ,and thereafter, transmitted to the external memory
1302
through the DMA bus
1301
by the control of the DMA control unit
1305
. As the encoding object video size after performing the resolution conversion, for example, QCIF, which is constituted by horizontal 176 pixels×vertical 144 pixels, or CIF, which is constituted by horizontal 352 pixels×vertical 288 pixels or the like are employed. The processor unit
1303
divides the encoding object video into rectangular regions of horizontal 16 pixels×vertical 16 pixels or horizontal 8 pixels×vertical 8 pixels, to take in the result into the encoding/decoding unit
1304
, and thereafter, performs the encoding processing, and stores the coded data in the external memory
1302
. When performing DMA for the encoding object video from the external memory
1302
to the encoding/decoding unit
1304
in the processor unit
1303
, when the processor
1303
sets the setting information for generating a rectangular access address to the DMA setting holding unit
1306
, the two dimensional address generating unit
1307
generates an address of the external memory
1302
in which data of the rectangular region are stored by employing the setting information. The two dimensional address generating unit
1307
for generating the rectangular access address can be realized by a construction disclosed in Japanese Published Patent Application No. Hei.4-218847. That is, the two dimensional address generating device
1307
is constituted to have an accumulation register for writing the address value that is employed actually as well as a first to N-th accumulation registers which are independent in each scan direction and, it is constructed such that, when the scan direction is switched, the address value is calculated by that the incremental data of the scan direction is added to the accumulation register corresponding to the scan direction. Thereby, since N pieces of accumulation registers hold the results of the address calculation that is previously performed for that scan direction until the scan direction becomes the same scan direction next time, there is no need to calculate an start address and set the result to the accumulation register every time when the scan direction is switched, and therefore, it is possible to access multi-dimensional data of a part of multi-dimensional region among the multi-dimensional address region, successively.
Further, as for the decoding processing, coded data, stored in the external memory
1302
, which were transmitted from another video processing apparatus are direct memory accessed to the encoding/decoding unit
1304
in the processor unit
1303
, to be decoded in units of the rectangular region, and the decoded video data are stored in the external memory
1302
.
FIG. 14
is a diagram illustrating the video data stored in the external memory
1302
. In
FIG. 14
,
1400
denotes pixel data DMA performed from the video input/output unit
1300
to the external memory
1302
. The numbers in the circles represent pixel positions, in more detail, the upper numbers represent pixel positions in the horizontal direction and the lower numbers represent pixel positions in the vertical direction.
1401
denotes an effective video data region DMA performed from the video input/output unit
1300
to the external memory
1302
and, in this case, shows horizontal 176 pixels and vertical 144 pixels.
1402
denotes a first pixel data extended region which is obtained by copying a pixel data (0, 0) at the top-left corner of the effective video data region
1401
,
1403
denotes a second pixel data extended region which is obtained by copying a pixel data (0, 175) at the top-right corner of the effective video data region
1401
,
1404
denotes a third pixel data extended region which is obtained by copying a pixel data (143, 175) at the bottom-right corner of the effective video data region
1401
,
1405
denotes a fourth pixel data extended region which is obtained by copying a pixel data (143, 0) at the bottom-left hand corner of the effective video data region
1401
,
1406
denotes a fifth pixel data extended region which is obtained by copying a pixel data line at the top of the effective video data region
1401
,
1407
denotes a sixth pixel data extended region which is obtained by copying a pixel data line at the right corner of the effective video data region
1401
,
1408
denotes a seventh pixel data extended region which copies a pixel data line at the bottom of the effective video data region
1401
, and
1409
denotes an eighth pixel data extended region which copies a pixel data
Arita Miki
Kohashi Yasuo
Kuromaru Shunichi
Moriiwa Toshihiro
Nakajima Hiromasa
Kostak Victor R.
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P.
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