Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1998-09-04
2001-12-04
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C348S399100, C348S402100, C348S439100, C348S715000, C348S510000, C348S511000, C348S423100, C348S432100, C348S460000, C348S467000, C348S512000
Reexamination Certificate
active
06326960
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a decoder and, more particularly, to a method and apparatus for video output phase control in a decoder.
BACKGROUND OF THE INVENTION
A typical decoder buffers data streams during variable and fixed delay. In particular, the depth of a buffer for variable delay is generally related to the delay in the decoder at a particular point in time. Also, in a typical decoder such as for an MPEG/MPEG2 (MPEG1 or MPEG2) decoder, variable and fixed delays can require significant buffering (e.g., system memory).
Thus, there remains a need for an efficient approach for buffering variable and fixed delays in a decoder. In particular, it would be desirable to provide an improved method and apparatus that efficiently utilizes memory in a decoder.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method and apparatus for video output phase control in a decoder. In one embodiment, the decoder includes a timer, a counter, and a comparator. If the time required to display video data is a fixed time interval (or delay), then the comparator can be set to this expected time delay such that when the current time in the timer is equal to the time programmed in the comparator, the comparator sends a signal to reset the counter. The timer is programmed to compare the local time with a particular time that represents the presentation time minus the fixed delay of the decoder. Accordingly, video output phase control is provided and efficient buffering for variable and fixed delays in the decoder is provided.
Other aspects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.
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Hjerpe Richard
Kwok Edward C.
National Semiconductor Corporation
Skjerven Morrill & MacPherson LLP
Zamani Ali A.
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