Static information storage and retrieval – Addressing – Combined random and sequential addressing
Patent
1994-12-12
1996-11-26
Zarabian, A.
Static information storage and retrieval
Addressing
Combined random and sequential addressing
365219, 36523005, G11C 800
Patent
active
055792758
ABSTRACT:
A video memory system includes a RAM for storing fixed image data at partial portions, two SAMs each split into at least first and second portions each for transferring a series of data simultaneously to the RAM, without synchronism with each other, a transferring section for transferring data from/to the second portion of the SAM to/from the RAM, when the first portion of the SAM is being accessed in series, and address designating section for determining a head address for serial access in the first portion of the SAM and a final address at which the serial access in the first portion is shifted to serial access in the second portion of the SAM. When two different image data are displayed simultaneously on a display, as when an inserted picture is required to be displayed on a background, it is possible to arrange the image data at predetermined area of the memory, irrespective of the position of the inserted picture on the display.
REFERENCES:
patent: 5065369 (1991-11-01), Toda
patent: 5185724 (1993-02-01), Toda
patent: 5247484 (1993-09-01), Watanabe
patent: 5257237 (1993-10-01), Aranda
patent: 5319603 (1994-06-01), Watanabe
Kabushiki Kaisha Toshiba
Zarabian A.
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