Video memory controller with dynamic bus arbitration

Details Video memory controller with dynamic bus arbitration Video memory controller with dynamic bus arbitration

1997-08-27

1999-05-11

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Interface

711151, 711158, G06F13/16

Patent

active

059032839

ABSTRACT:
In a video controller system including a video memory and first and second pluralities of functional circuits which access the video memory, requests for access to the video memory among more than one of the functional circuits are arbitrated by two levels of arbitration. In the first level of arbitration, a buffer in each of said first pluralities of functional circuits temporarily stores data read from or to be written to the video memory. A priority is assigned to requests for access from each of the functional circuits. A low limit and a high limit are assigned for each of the buffers. Requests for access to the video memory from all of the functional circuits are monitored. Each of the buffers is monitored to indicate whether the amount of data in each buffer is below the low limit or above the high limit. Access to the video memory is granted first to any requesting ones of the functional circuits whose buffers are below the low limit in order of the assigned priority. Access to the video memory is next granted to any requesting ones of the functional circuits whose buffers are not below the low limit and not above the high limit in order of the assigned priority. In the second level of arbitration, related functional circuits in the second plurality of functional circuits are grouped together under a selected functional circuit from said first plurality of functional circuits, and are provided data from the buffer in the selected functional circuit from the first plurality of functional circuits according to a priority determined by any of several methods known in the art.

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