Computer graphics processing and selective visual display system – Display peripheral interface input device – Light pen for fluid matrix display panel
Reexamination Certificate
1997-10-09
2001-08-28
Luu, Matthew (Department: 2672)
Computer graphics processing and selective visual display system
Display peripheral interface input device
Light pen for fluid matrix display panel
C345S182000, C348S581000, C348S448000, C348S458000
Reexamination Certificate
active
06281873
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to video processing and more particularly to a vertical scaling process and apparatus.
2. Description of the Prior Art
It is a well known problem to convert raster scanned RGB video to a television format. RGB video in this context includes VGA, SVGA and XVGA; these are examples of component video formats for personal computers. RGB stands for the red, green and blue channels that comprise the complete RGB video signal. Television refers to the NTSC, PAL and SECAM television timing standards which are used in television sets. Common television data formats are composite video and S-video (Y/C). Most commonly, RGB video from personal computers uses a non-interlaced (progressive) scan while television uses interlaced scan. In e.g. NTSC television there are 525 horizontal scan lines of analog video data per frame divided into even and odd interlaced fields of 262.5 lines each. Each NTSC television frame thus includes an odd field and an even field which are interlaced to form one frame. The refresh rate for NTSC television is 30 frames per second (30 Hz) while the fields are refreshed at twice the frame rate which for NTSC is 60 Hz.
Television sets use a technique known as overscan to insure that the picture fills the entire video display, (e.g. picture tube) framed within the bezel. Unfortunately, this overscan technique, when applied to the output video signal from a personal computer, may result in a display image having truncated upper and lower portions as well as truncated left and right portions. For a computer display image such truncation is not acceptable since useful information may appear in the truncated portions. Thus, in order to display a high resolution personal computer video image on a television set, the size of the image must be decreased to make the picture viewable within the bezel. For most commercially sold television sets, vertical overscan is about 12%. Thus if the personal computer output display image is vertically scaled to fit within 400 horizontal scan lines and the length of the active video scaled by 0.88, all of the display image would appear on a television without being truncated due to overscan.
Another problem encountered with displaying VGA video on a television set is caused by the lower frame rate of television, (50 Hz for PAL, 60 Hz for NTSC) contrasted with the relatively high refresh rates of VGA, is typically 60-75 Hz.
U.S. Pat. No. 5,510,843 issued to Keene et al., incorporated herein by reference, describes this situation and an attempted solution. Keene et al, FIGS. 6 and 7A illustrate a filtering technique which provides vertical scaling, which means reducing the number of input lines to a fewer number of output lines in the output video signal. (“Lines” refers to video horizontal scan lines.) Keene et al., describes vertical scaling to reduce the 480 VGA lines to 400 lines for a television output signal. Note that in a typical NTSC television set (or monitor) a total of only 400 horizontal scan lines are available for the actual active video, allowing for the vertical blanking interval and overscan.
Since therefore it is often desirable to scale down or shrink video frames in a horizontal or vertical direction, the scaling typically involves selectively reducing the number of pixels or rows in the frame.
Hence, while prior art solutions are available to the scaling problem, there is need for improvement, especially in vertical scaling, because most prior art vertical scaling methods require the support of external video memory, increasing cost and complexity. One prior approach, using linear interpolation does not include the flicker filter function. A decimating linear interpolator requires two line stores while the following flicker filter requires two line stores. Consequently, four line stores are needed. Also, certain prior implementations produce artifacts such as intensity modulation in the vertical direction when the incoming column of pixels has alternate pixels on/off.
SUMMARY
This disclosure is directed to a line rate vertical scaling process and apparatus. The vertical scaling is the reduction of M active video lines to N active video lines by e.g. polyphase filtering and matching the active period of the M lines to the active period of the N lines.
The line rate vertical scaling includes: (1) A polyphase filter to reduce the number of lines. In one example, nine lines are filtered down to eight lines. It may be easier in other embodiments to filter eight lines to seven. Also the whole process may be programmable, for example, scaling with a range from 32/64 to 63/64 based upon repeating the scaling sequence every 64 lines. (2) Making the vertical active period of the incoming video source equal to the active video period of the outgoing TV signal. The horizontal scan rate is increased by 9/8 in one example. If the scaling factor is 7/8, then the frequency is increased by 8/7. (3) Flicker filtering is inherent in one implementation because the filtering is low pass with polyphases.
Thus in accordance with this invention, for line rate vertical scaling of video signals, scaling and filtering are combined into a single process, using a polyphase filter. The vertical scaling is implemented by processing columns of pixels. Only a few pixels, e.g. four, are processed at any one time. The actual processing involves taking four successive pixels which in the image are vertically adjacent and convolving them with an adaptive kernel with weights (filter coefficients) preset by the line count to correctly interpolate the outgoing video line. Conversion in this case of 480 incoming active video lines to e.g. 428 outgoing active video lines is executed modulo 9. Thus for every 9 (m) incoming lines, there are 8 (n) outgoing lines. Each outgoing line is thereby the weighted sum of the nearby incoming lines.
In one embodiment, a field buffer memory (e.g. frame store) is used in order to provide timing for dropped lines, and to accommodate a range of incoming vertical refresh rates and to accommodate standard VGA timing. In another embodiment the field buffer memory is omitted and a much smaller FIFO (first in—first out) memory for only one or two lines is substituted. Therefore in this latter case while frame rate conversion is not available, the circuit may easily be implemented on a single integrated circuit. This latter embodiment requires that the incoming video frame rate equals the output video field rate and that the incoming active video period equals the outgoing active video period.
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Derwent Abst. 93-167660/20.
Chem. Abst. 195363q. for DE 2,342,907.
Derwent Abst. 95-270481/36 for EP 666288.
Fairchild Semiconductor Corporation
Klivans Norman R.
Luu Matthew
Sajous Wesner
Skjerven Morrill & MacPherson LLP
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